Method of forming semiconductor device
A semiconductor and device technology, applied in the field of semiconductor device formation, can solve the problems that the electrical properties of semiconductor devices need to be improved, and achieve the effects of preventing plasma-induced damage, improving electrical performance and reliability, and avoiding electrochemical corrosion
Active Publication Date: 2019-11-12
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology
[0004] However, despite the introduction of a high-k metal gate process, the electrical performance of semiconductor devices formed by the prior art still needs to be improved
Method used
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Embodiment Construction
[0031] It can be seen from the background art that the electrical performance of semiconductor devices formed in the prior art still needs to be improved.
[0032] It has been found through research that in order to meet the requirements of improving the threshold voltage (Threshold Voltage) of NMOS tubes and PMOS tubes at the same time, different metal materials are usually used as the work function (WF, WorkFunction) layer materials of the metal gates of NMOS tubes and PMOS tubes, so The metal gates of the NMOS transistor and the PMOS transistor are formed successively, instead of forming the metal gates of the NMOS transistor and the PMOS transistor at the same time.
[0033] In one embodiment, refer to figure 1, providing a substrate 100, the substrate 100 includes a PMOS region, an NMOS region and other device regions; a first dummy gate 111 is formed on the substrate 100 in the NMOS region, and a second dummy gate 121 is formed on the substrate 100 in the PMOS region, ...
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The invention provides a forming method of a semiconductor device. The method comprises the steps as follows: a first mask layer is formed on a substrate in a third region, the top surface of an interlayer dielectric layer in a first region, the top surface of a first dummy gate, the top surface of an interlayer dielectric layer in a second region and the top surface of a second metal gate; a second mask layer is formed on the surface of the first mask layer at the upper part of the second metal gate and the material of the second mask layer is different from that of the first mask layer; a graphic layer is formed on the substrate in the third region; the first mask layer in the first region and the first dummy gate are etched and removed by employing the graphic layer as a mask, a first opening is formed in the interlayer dielectric layer in the first region, the second mask layer in the second region is etched in the process of forming the first opening and the top surface of the second metal gate is covered with the first mask layer; the first mask layer on the top surface of the second metal gate is removed; and a first metal gate for filling the first opening is formed. According to the forming method of the semiconductor device, the electrical property and the reliability of the semiconductor device are improved.
Description
technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor device. Background technique [0002] At present, in the manufacturing process of semiconductor devices, a P-type metal oxide semiconductor (PMOS, P type Metal Oxide Semiconductor) tube, an N-type metal oxide semiconductor (NMOS, N type Metal Oxide Semiconductor) tube, or a combination of a PMOS tube and an NMOS tube The formed Complementary Metal Oxide Semiconductor (CMOS, Complementary Metal Oxide Semiconductor) tube is the main device constituting the chip. [0003] With the continuous development of integrated circuit manufacturing technology, the technology nodes of semiconductor devices are continuously reduced, and the geometric dimensions of devices are continuously reduced following Moore's law. When the device size is reduced to a certain extent, various secondary effects caused by the physical limit of the devic...
Claims
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IPC IPC(8): H01L21/8238H01L21/311H01L21/28
CPCH01L21/28H01L21/31105H01L21/31144H01L21/8238
Inventor 张海洋张城龙纪世良
Owner SEMICON MFG INT (SHANGHAI) CORP