This application belongs to the field of display driving technology, specifically relating to a gate
driving circuit, a fabrication method, and a display panel. The gate
driving circuit includes N cascaded GOA circuit units; a reset
signal line disposed on any side near the GOA circuit unit, electrically connected to the gate of a reset
transistor, and located on the same
metal layer as the gate of the reset
transistor; a
cathode signal line disposed on the same side as the reset
signal line and away from the GOA circuit unit; the
cathode signal line electrically connected to the drain or source of the reset
transistor, and located on the same
metal layer as the source or drain of the reset transistor; and multiple
clock signal lines disposed between the reset signal line and the
cathode signal line, electrically connected to the
clock signal line of the GOA circuit unit. This application eliminates the presence of ITO vias on the low-level
signal lines, avoiding
electrochemical corrosion of the ITO layer in high-temperature and high-
humidity environments, thus improving the stability of the gate
driving circuit.