Dielectric nano structure preparation method compatible with CMOS process

Abstract

The invention provides a dielectric nano structure preparation method compatible with a CMOS process. The method comprises the following steps: a hard mask material layer is formed on a target dielectric material; a lithography technology is adopted to form a lithography pattern on the hard mask material layer; the lithography pattern is used as a mask, a dry etching technology is adopted to etch the hard mask material layer, and a hard mask pattern is formed; the hard mask pattern is used as a mask, and the dry etching technology is adopted to etch the dielectric material to form a dielectric nano structure pattern; and the lithography and the hard mask material layer are removed. The nano-scale pattern can be precisely transferred on the silicon dioxide or silicon nitride dielectric material simply and efficiently, and the dielectric nano structure is formed. The production process complexity and the preparation cost can be effectively reduced, and an extremely important role is played in quickly preparing various dielectric nano structures.

Description

technical field [0001] The invention relates to the field of nano-manufacturing, in particular to a method for preparing a dielectric nano-structure compatible with a CMOS process. Background technique [0002] According to the requirements of Moore's Law, the feature size of VLSI continues to shrink driven by advanced technology. At present, the most advanced semiconductor integrated circuit manufacturing has reached the 22nm technology node, and the 14nm technology node is about to be mass-produced. They adopt A new three-dimensional structure has been developed. The nano-device structure transitions from a planar to a three-dimensional structure, and the gradual reduction of line width poses a huge challenge to the photolithography and etching process. In the case that extreme ultraviolet (EUV) lithography has been lagging behind and has not been introduced to the market on schedule, after the 32nm process node, 193nm immersion lithography technology combined with double...

AI Technical Summary

Problems solved by technology

Although the industry has developed some corresponding mask materials, mainly carbon-containing materials such as amorphous carbon materials, spin-coated carbon and carbon-silicon materials, etc., however, the introduction of these new materials requires a lot for general manufacturing companies or research institutions. It costs more to purchase related equipment, which undoubtedly increases the manufacturing cost

In addition, the complex mask structure will also lead to complex process integration, which also puts considerable pressure on the manufacturing cost. In addition to the above-mentioned complex mask structure, in some manufacturing processes, it is often necessary to introduce metal masks , which will lead to metal contamination, making it not compatible with CMOS process

Images