Fin type field effect transistor formation method

A fin field effect transistor and fin technology are applied in semiconductor devices, electrical components, circuits, etc., and can solve the problem that the electrical performance of the fin field effect transistor needs to be improved.

Inactive Publication Date: 2017-04-05
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, the electrical performance of the fin field effect transistor formed by the prior art needs to be improved

Method used

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  • Fin type field effect transistor formation method
  • Fin type field effect transistor formation method
  • Fin type field effect transistor formation method

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Embodiment Construction

[0034] It can be seen from the background art that the electrical performance of the fin field effect transistor formed in the prior art needs to be improved.

[0035] It has been found through research that the distance between the bottom of the fin and the gate structure of the fin field effect transistor is relatively long, the ability of the gate structure to control the bottom of the fin is weak, and the doping concentration of the fin is small, and the channel The space charge region of the area is widened under the electric field, and the space charge region of the source region and the drain region are connected, resulting in a punch through phenomenon between the source region and the drain region at the bottom of the fin field effect transistor, resulting in a fin field effect The electrical performance of the tube is low. And in order to improve the electrical performance of the fin field effect transistor, the dopant is usually doped in the substrate, the dopant in...

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Abstract

The invention provides a fin type field effect transistor formation method comprising the steps that a protective layer is formed on the surface of a substrate, and the top part of the protective layer is lower than the top part of a first fin part and the top part of a second fin part; a first side wall is formed on the surface of the side wall of the first fin part higher than the top part of the protective layer; a second side wall is formed on the surface of the side wall of the second fin part higher than the top part of the protective layer; partial thickness or all the thickness of the protective layer is removed; a first epitaxial layer is formed on the surface of the side wall of the exposed first fin part, and the first epitaxial layer includes first penetration prevention ions; a second epitaxial layer is formed on the surface of the side wall of the exposed second fin part, and the second epitaxial layer includes second penetration prevention ions; annealing is performed on the first epitaxial layer and the second epitaxial layer; the first side wall and the second side wall are removed; and a dielectric layer is formed on the substrate, the surface of the first epitaxial layer and the surface of the second epitaxial layer. The electrical performance of the formed fin type field effect transistor can be improved by the fin type field effect transistor formation method.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a fin field effect transistor. Background technique [0002] With the continuous development of semiconductor process technology, the development trend of semiconductor process nodes following Moore's Law continues to decrease. In order to adapt to the reduction of process nodes, the channel length of MOSFET field effect transistors has to be continuously shortened. The shortening of the channel length has the advantages of increasing the die density of the chip and increasing the switching speed of the MOSFET field effect tube. [0003] However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control ability of the gate to the channel becomes worse, and the gate voltage pinches off the channel. The difficulty is also increasing, making the pheno...

Claims

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Application Information

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IPC IPC(8): H01L21/8238
CPCH01L21/823821H01L29/66803
Inventor 李勇
Owner SEMICON MFG INT (SHANGHAI) CORP
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