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Metal oxide semiconductor field effect transistor based on multi-grid structure and preparation method thereof

A metal oxide half-field and multiple gate technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of reduced operating current and difficulty in meeting usage requirements, and achieves maintaining operating current and suppressing collapse Phenomenon, the effect of uniform electric field distribution

Active Publication Date: 2017-04-05
湖南三安半导体有限责任公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] At present, for a MOSFET with a planar structure, the amount of current it can withstand and the breakdown voltage are related to the length and width of its channel. Therefore, in circuit design, the distance between the gate and the drain is usually elongated to Increase the breakdown voltage, but its working current will also be relatively reduced, which is difficult to meet the actual use needs

Method used

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  • Metal oxide semiconductor field effect transistor based on multi-grid structure and preparation method thereof
  • Metal oxide semiconductor field effect transistor based on multi-grid structure and preparation method thereof

Examples

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Embodiment 1

[0035] refer to figure 1 , the metal oxide semiconductor field effect transistor 100 of the present embodiment comprises a P-based N-channel substrate 110, the substrate 110 is a P-type silicon semiconductor, and two N+ regions 111 are formed by N-type heavy doping and are located between the two N+ regions. Several N-type doped regions 112 between the regions 111. The sources 120 and 130 are respectively drawn above the two N+ regions 111, and a number of oxide layers 140 are arranged at intervals between the source electrodes 120 and the drain electrodes 130, and sub-gates 150 are arranged one by one above the oxide layers 140, that is, the sub-gates The electrodes 150 are arranged at intervals from the source 120 to the drain 130 to form a multiple gate structure, and the gaps between adjacent sub-gates 150 correspond to the N-type doped regions 112 one-to-one. Each sub-gate 150 includes a polysilicon layer 151 and an electrode layer 152 disposed above the polysilicon laye...

Embodiment 2

[0047] refer to figure 2 , the metal oxide semiconductor field effect transistor 200 of the present embodiment comprises a substrate 210 of a P-based N-channel, the substrate 210 is a P-type silicon semiconductor, and two N+ regions 211 are formed by N-type heavy doping and are located between the two N+ regions. Several N-type doped regions 212 between the regions 211. The sources 220 and 230 are respectively drawn above the two N+ regions 211, an oxide layer 240 is formed between the source 220 and the drain 230, and a plurality of sub-gates 250 are arranged above the oxide layer 240, and these sub-gates 250 are formed from the source 220 to the drain 230. The drain electrodes 230 are arranged at intervals to form a multiple gate structure, and the gaps between adjacent sub-gates 250 correspond to the N-type doped regions 212 one-to-one. Each sub-gate 250 includes a polysilicon layer 251 and an electrode layer 252 disposed above the polysilicon layer 251 . A passivation l...

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Abstract

The invention discloses a metal oxide semiconductor field effect transistor based on a multi-grid structure. The metal oxide semiconductor field effect transistor comprises an N-based P channel or P-based N channel substrate. A source electrode and a drain electrode are respectively led out of the two P+ regions of the N-based P channel substrate or the two N+ regions of the P-based N channel substrate. An oxide layer is arranged between the source electrode and the drain electrode. Multiple sub-grids are arranged on the oxide layer. The sub-grids are discretely arranged in a spacing way from the source electrode to the direction of the drain electrode so as to form the multi-grid structure, wherein each sub-grid comprises a polysilicon layer and an electrode layer which is arranged on the polysilicon layer. The substrate also comprises multiple doping regions which are the same type of the channel and arranged between the two P+ regions or the two N+ regions. Each doping region is corresponding to the position below the gap of the adjacent sub-grids in a one-to-one way. Compared with the conventional single grid structure, an electric field can be effectively scattered by multiple grids so that the phenomenon of collapse voltage caused by the strong electric field generated beside the grids can be suppressed. The invention also provides a preparation method of the transistor.

Description

technical field [0001] The invention relates to a semiconductor device, in particular to a metal-oxide-semiconductor field-effect transistor based on a multiple gate structure and a preparation method thereof. Background technique [0002] In the currently popular transistors, whether silicon (Si), silicon carbide (SiC) or gallium nitride (GaN) is used as a switching device, how to suppress gate The collapse phenomenon caused by the strong electric field generated by the high voltage is the subject of many research units. [0003] Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is a field effect transistor widely used in analog circuits and digital circuits. According to the polarity of the channel, it is divided into two types: N-channel and P-channel. Taking the P-based N-channel enhanced type as an example, a P-type silicon semiconductor is used as a substrate, and two N+ regions are diffused on its surface, and then covered with a silicon oxide insulating lay...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L29/423H01L21/336
CPCH01L29/42356H01L29/66484H01L29/78
Inventor 庄秉翰叶念慈
Owner 湖南三安半导体有限责任公司
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