Dummy device assisted sensitivity amplifier circuit

Abstract

The invention discloses a dummy device assisted sensitivity amplifier circuit. The dummy device assisted sensitivity amplifier circuit comprises a first phase inverter, a second phase inverter, a third phase inverter, a first PMOS (P-channel Metal Oxide Semiconductor) transistor, a second PMOS transistor and a first NMOS (N-channel Metal Oxide Semiconductor) transistor; an output end of the first phase inverter is connected with an input end of the second phase inverter; an output end of the second phase inverter is connected with an input end of the first phase inverter; the dummy device assisted sensitivity amplifier circuit further comprises a second NMOS transistor and a third NMOS transistor; a source electrode and a drain electrode of the second NMOS transistor are both connected with the output end of the first phase inverter; a source electrode and a drain electrode of the third NMOS transistor are both connected with the output end of the second phase inverter; and grids of the second NMOS transistor and the third NMOS transistor are both connected with an input end of the third phase inverter. The dummy device assisted sensitivity amplifier circuit effectively improves the influences that the traditional sensitivity amplifier reduces the initial pressure difference because of capacity coupling, the yield and the speed of the sensitivity amplifier are improved, and moreover, the area of the original circuit layout is not affected.

Description

technical field [0001] The invention relates to the technical field of storage circuits, in particular to a dummy device auxiliary sense amplifier circuit. Background technique [0002] The sensitive amplifier circuit is the core circuit of the memory, especially the static memory, which amplifies the small voltage difference on the bit line to a logic level for reading, thereby effectively reducing the read power consumption and read delay. The pseudo-device is a device placed around the core circuit without any connection and function to ensure the uniformity of the core circuit process. [0003] Conventional sense amplifier circuits such as figure 1 As shown, its basic workflow is: [0004] BL / BLB will gradually generate a voltage difference due to the memory cell reading. When the voltage difference is large enough, ENSAB changes from 1 to 0, and the sense amplifier starts. Such as figure 2 DL and DLB in , are the voltages connected by BL / BLB through open MP1 and M...

AI Technical Summary

Problems solved by technology

[0005] However, there are two capacitive coupling problems in the entire amplification process, that is, when the sense amplifier is started, it will cause interference to the initial signal difference, affect the actual differential voltage of the amplification, and thus affect the yield and speed of the sense amplifier

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