A kind of power semiconductor device and its manufacturing method
A technology for power semiconductors and manufacturing methods, which is applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as high doping concentration and inability to achieve, and achieve low process cost, low power consumption, and reduced on-state The effect of pressure drop
Active Publication Date: 2019-12-27
ZHUZHOU CRRC TIMES SEMICON CO LTD
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Problems solved by technology
[0011] In view of this, the object of the present invention is to provide a power semiconductor device and a manufacturing method thereof, which can overcome the fact that the N well (carrier storage layer) of the existing trench gate power semiconductor device cannot be doped through a diffusion process. Technical issues with higher doping concentrations
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specific Embodiment
[0086] A specific embodiment of a method for manufacturing a power semiconductor device as described above, comprising the following steps:
[0087] S101: First, perform implantation and diffusion doping of the P-base region 1 on the basis of the N-substrate 2, as shown in the attached Figure 11 shown.
[0088] Step S101 further includes the following process:
[0089] S1011: Through high temperature oxidation, on the basis of N-substrate 2, a sacrificial oxide layer (SiO 2 , silicon dioxide) 10, the thickness of the sacrificial oxide layer 10 is 100A to 600A, preferably 300A;
[0090] S1012: Coating a layer of photoresist 9 on the sacrificial oxide layer 10, then exposing, and removing the photoresist 9 above the active area (cell area) of the device to form a P-base region injection window;
[0091] S1013: performing P-type ion implantation, and removing the remaining photoresist 9 on the device surface;
[0092] S1014: Carry out high-temperature advancement (diffusion pr...
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The invention discloses a power semiconductor device and a manufacturing method thereof. A power semiconductor device comprises a P-base region, an N-substrate, an N trap, polysilicon gates, N+source electrode regions, a P+ohmic contact region, emitting electrode metal electrodes and gate oxide layers. The power semiconductor device is of a groove gate structure. Each groove of the groove gate structure has a first depth and a second depth, wherein the first depth is the depth obtained through the first groove etching and N trap injection; the first depth is larger than or equal to the junction depth of the P-base region, and smaller than the depth of the N trap; and the second depth is the depth of the corresponding groove. According to the invention, the technical problem can be overcome that quite high doping concentration cannot be achieved since the doping of a N trap (a carrier storage layer) of the current groove gate power semiconductor device is achieved through the diffusion technology.
Description
technical field [0001] The present invention relates to the technical field of power semiconductors, in particular to a power semiconductor IGBT (Insulated Gate Bipolar Transistor, insulated gate bipolar transistor) device and a manufacturing method thereof. Background technique [0002] In the prior art, in order to optimize the on-state voltage drop and turn-off loss of the power semiconductor device and reduce the power consumption of the device, a carrier storage layer (hole blocking layer) structure is generally used, which is also called " N-Enhancement Layer" (N-strengthening layer) and "Carrier Storage N Layer" (N-type carrier storage layer). as attached figure 1 As shown, it is an IGBT based on a planar gate structure of a carrier storage layer. The structure is surrounded by a layer of N-enhanced layer 12 under the P-base region. In the figure, 7 is the emitter metal electrode, and 11 is the collector metal electrode. The applicant filed an application on Decembe...
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IPC IPC(8): H01L29/739H01L21/331H01L29/423
CPCH01L29/4236H01L29/66325H01L29/7393
Inventor 刘国友覃荣震黄建伟张泉朱利恒戴小平
Owner ZHUZHOU CRRC TIMES SEMICON CO LTD