A multi-channel clock adjustment method based on phase self-synchronization technology

Abstract

Disclosed is a multichannel clock adjusting method based on a manuscript to be translated with translator based on similarity matching algorithm. The method comprises the following steps that a VCXO is adopted for providing a working clock source, a multi-channel synchronous clock needed by the system is output after smoothing, clock circuit internal fractional frequency, phase locking, synchronous and other function modules, multichannel clock signals can be transmitted according to the system demand by adopting a single-end differential signal mode, finally, the signals are provided to ADC1 to ADCn for high-speed data collection, after the multi-channel ADC completes data collection, the collected data is transmitted to a processor, the synchronous detection module performs synchronous error analysis on all the collected channel data, the analysis result is transmitted to a clock source circuit through the synchronous feedback mechanism for clock phase adjustment, clock phase adjustment is completed, and data collection synchronization is ensured. The multichannel clock adjusting method has the advantages that no special synchronous testing device is depended on, the adjusting precision is high, the system synchronous design difficulty can be lowered, and the engineering application is easy.

Description

Technical field [0001] The present invention belongs to the technical field of electronic circuit, and is related to a multiplex clock adjustment method. Background technique [0002] The rate of communication system is constantly increasing, and the clock has become a key factor affecting system performance. In particular, in the field of multi-channel, array signal processing, the clock is jitter size, phase consistency to determine the signal-to-noise ratio of the system's data acquisition, so that the effective number of ADC converters is reduced, which affects multiple ADCs. Synchronous collection. If the phase of the sampling clock is deviated, it is finally reflected to data between the different channels there is a certain phase error. The detection and adjustment of multi-channel data acquisition consistency errors in array signal acquisition systems can further improve synchronization performance from the perspective of the system design. [0003] The design method in t...

AI Technical Summary

Problems solved by technology

However, as the operating frequency of the system clock is further increased, and affected by various factors such as PCB processing technology, precision of resistive capacitors, component differences, and interference on the PCB transmission path, the disadvantages caused by the clock transmission path of the array signal acquisition system Synchronization issues are growing

Moreover, due to the uncertainty of processing process errors and the uncertainty of time delays caused by transmission paths, it is difficult to fully compensate through layout design in the early stage

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