Method for manufacturing trench gate device with shielded gate

Abstract

The invention discloses a manufacturing method for a groove gate device with a shielding gate. The manufacturing method comprises the steps of performing photoetching on a first epitaxial layer to form a groove; sequentially forming a first oxide layer and a first layer of poly-silicon; etching the first layer of poly-silicon to obtain a poly-silicon shielding gate; depositing a second oxide layer by high density plasma chemical vapor deposition (HDP CVD) to fill a part of the top of the groove; performing wet etching on the oxide layer so that a part thickness of the second oxide layer is reserved only on a surface of the poly-silicon shielding gate in the groove; depositing a third oxide layer by HDP CVD so as to perform non-hole complete filling on the top of the groove; performing wet etching the oxide layer to form a poly-silicon isolation oxide layer which is overlapped by the second oxide layer and the third oxide layer, wherein the second oxide layer and the third oxide layer are reserved on the surface of the poly-silicon shielding gate; forming a gate dielectric layer; and forming a second layer of poly-silicon and assembling a poly-silicon gate. By the manufacturing method, the thickness uniformity of the poly-silicon isolation oxide layer is improved, hole generation is prevented, and the isolation performance of the poly-silicon isolation oxide layer is improved.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for manufacturing a trench gate device with a shielding gate. Background technique [0002] Such as Figure 1A to Figure 1J As shown, it is a schematic diagram of the device structure in each step of the manufacturing method of the existing trench gate device with a shielding gate; the existing manufacturing method of the trench gate device with a shielding gate includes the following steps: [0003] Step 1, such as Figure 1A As shown, a first epitaxial layer 101 is provided, and a hard mask layer 102 is formed on the surface of the first epitaxial layer 101, and the hard mask layer 102 is composed of an oxide layer. A trench 103 is formed in the gate forming region of the first epitaxial layer 101 by photolithography. [0004] Generally, the first epitaxial layer 101 is formed on the surface of a semiconductor substrate, the semiconduct...

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Problems solved by technology

[0024] However, for the pitch smaller than 1.5 microns, especially for the upper and lower structure shielded gate trench MOSFET devices with a pitch smaller than or equal to 1.0 microns, due to the limitation of the aspect ratio of filling the HDP CVD oxide layer, cavities 201 and 202 will be generated in step five, the above process The method is very easy to cause uneven thickness of the polysilicon isolation oxide layer 106 between the control gate, that is, the polysilicon gate 108 and the polysilicon shielding gate 105 or even a short circuit.

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