LDO (low-dropout) Circuit having transient reinforcing structure unit and having no off-chip capacitor
A technology with no off-chip capacitors and enhanced structure, applied in the direction of adjusting electrical variables, control/regulating systems, instruments, etc., can solve the problems of high power consumption and large chip area, and achieve the purpose of reducing power consumption, reducing chip area and simple structure. Effect
Active Publication Date: 2017-10-24
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT +1
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Problems solved by technology
However, the existing transient enhancement circuit and a set of current mirror circuits can only realize the detection and adjustment of one of the increase or decrease of the LDO output voltage, and the adjustment of the two conditions requires two sets of current mirror structures, and the chip area Larger, higher power consumption
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[0025] Attached below figure 1 and 2 , the specific embodiment of the present invention will be further described in detail. It should be noted that the drawings are all in a very simplified form, using imprecise scales, and are only used to facilitate and clearly achieve the purpose of assisting in describing the present embodiment.
[0026] see figure 1 , figure 1 Shown is a schematic circuit diagram of the low dropout linear voltage regulator without off-chip capacitors of the present invention. As shown in the figure, the LDO circuit without off-chip capacitors includes an error amplifier EA, a single-input amplifier A, an output stage unit 1 and a transient enhancement structural unit SRE.
[0027] In an embodiment of the present invention, the error amplifier EA has a non-inverting input terminal, an inverting input terminal and an output terminal, and the non-inverting input terminal is connected to a reference voltage signal. Specifically, the reference voltage si...
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An LDO (low-dropout) circuit having a transient reinforcing structure and having no off-chip capacitor comprises an error amplifier, a single-input amplifier, an output-level unit, and the transient reinforcing structure unit; the output-level unit has a power MOS (metal oxide semiconductor) transistor M1 and first and second feedback resistors connected sequentially in series, the input end of the transient reinforcing structure unit is connected with the output end of the LDO circuit with no off-chip capacitor, and two output ends of the transient reinforcing structure unit are connected with a gate of the power MOS transistor M1 and the bias input end of the single-input amplifier respectively, wherein the error amplifier is used for comparing a feedback voltage signal from the output tend of the LDO circuit with no off-chip capacitor to a reference voltage signal, and amplifying and outputting compared error results by the single-input amplifier; the transient reinforcing structure detects output voltage of the LDO circuit with no off-circuit capacitor, and adjusts voltage of the power MOS transistor M1 according to changes in the output voltage of the LDO circuit with no off-circuit capacitor, and therefore, the output voltage of the LDO circuit with no off-circuit capacitor is restored quickly.
Description
technical field [0001] The present invention relates to the field of integrated circuit technology, in particular to the field of CMOS analog integrated circuit design, in particular to a low dropout regulator (LDO for short) circuit design with a transient enhancement structural unit and no off-chip capacitance . Background technique [0002] With the development of Complementary Metal Oxide Semiconductor (CMOS) integrated circuit technology, electronic products are more and more widely used in daily life, and they become an indispensable part of various fields. The increasingly miniaturized development goal of CMOS integrated circuit chips determines that low power consumption and high integration have become an important direction for the development of CMOS integrated circuits. [0003] LDO (Low Dropout Regulator, low dropout linear regulator) is widely used in CMOS integrated circuits, especially low power consumption circuit design. However, the common LDO will make ...
Claims
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IPC IPC(8): G05F3/26
CPCG05F3/262
Inventor 曾夕严慧婕张远段杰斌袁庆
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT