Three-dimensional daisy chain topology by aiming at multi-load DDRX (Double Data Rate) interconnection

Abstract

The invention discloses a three-dimensional daisy chain topology by aiming at multi-load DDRX (Double Data Rate) interconnection. By use of the topology, the nonideal effect of an interconnection linkcan be lowered, and signal transmission quality is improved. On the basis of the three-dimensional space structure of the DDRX, two classes of routing layers, including a routing layer A and a routing layer B, are alternately arranged in the DDRX, wherein the routing layer A and the routing layer B are independently next to a surface layer and a bottom layer; and a signal flows through each loadthrough the routing layer A and the routing layer B in sequence, and the effective combination of a through hole and a transmission line in the three-dimensional DDRX space are utilized for reducingthe length of each load branch line so as to effectively reduce reflection among multiple load branch lines, reduce the influence of an nonideal effect and improve signal transmission quality. In addition, processing is carried out through a through hole backdrill and keep out to further reduce the own nonideal effect of the through hole.

Description

technical field [0001] The invention relates to the technical field of high-speed PCB (Printed Circuit Board) design, in particular to a three-dimensional daisy chain topology for multi-load DDRX interconnection. Background technique [0002] In the field of high-speed digital circuit design, the continuous improvement of DDRX storage capacity and access rate makes the non-ideal effect of the interconnection link obvious, mainly in three aspects: first, the transmission line effect causes signal delay, loss, etc.; second, the signal via hole The impedance discontinuity at the location leads to signal reflection; the third is the impedance discontinuity caused by the branch line and the multi-load effect causing signal reflection; these effects together cause frequent signal integrity problems, which restricts the design and implementation of high-speed multi-load DDRX interconnection. [0003] As an effective means to improve the signal quality of multi-load links, the daisy...

AI Technical Summary

Problems solved by technology

Under the influence of non-ideal effects, all kinds of signal reflections are intricate and superimposed on each other, which makes the quality of key signals deteriorate, such as the edge return groove, overshoot, undershoot, ringing, etc. of the clock signal at the receiving end, the receiving end address, control , The eye height and eye width of the eye diagram of the command line are reduced, etc., which eventually lead to problems such as DDRX working abnormally and data transmission errors

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