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Power buffer diode chip structure and manufacturing method thereof

A buffer diode and chip structure technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of unfavorable miniaturization integration, large number of electronic components, high cost, etc., and achieve the goal of saving circuit space and production cost Effect

Pending Publication Date: 2018-02-23
成都方舟微电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, with this circuit structure, the number of electronic components is large and the volume is large, which is not conducive to miniaturization and integration, and the cost is high

Method used

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  • Power buffer diode chip structure and manufacturing method thereof
  • Power buffer diode chip structure and manufacturing method thereof
  • Power buffer diode chip structure and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0039] Such as Figure 4 The shown chip structure of a power buffer diode includes a lower metal layer, a substrate 1 and an epitaxial layer 2 stacked sequentially from bottom to top, the substrate and the lower metal layer constitute an electrode of the power buffer diode, and the epitaxial layer A deep diffusion region 3 is formed on the 2, a well region 4 is formed on the deep diffusion region 3, a shallow diffusion region 5 is formed on the well region 4, a channel resistance region 6 is formed on the well region 4, The deep diffusion region and the shallow diffusion region are not in contact and are connected through the channel resistance region 6, that is, the two ends of the channel resistance region 6 are respectively connected to the deep diffusion region and the shallow diffusion region, and the conductivity of the epitaxial layer 2 and the well region 4 The type is the same as the conductivity type of the substrate, and the conductivity type of the shallow diffusio...

Embodiment 2

[0044]In this embodiment, the conductivity type of the substrate is P-type to illustrate the structure of the above-mentioned power buffer diode chip and its manufacturing method.

[0045] like Figure 5 Shown is a schematic diagram of the structure of a buffer diode chip using a P-type silicon substrate. In the figure, the buffer diode chip includes a silicon substrate doped with P-type impurities, a first epitaxial layer doped with P-type impurities; The second epitaxial layer; the deep diffusion region doped with N-type impurities; the well region doped with P-type impurities; the shallow diffusion region doped with N-type impurities; and the dielectric layer above the chip; metal layer, etc.; the anode of the snubber diode is on the lower metal layer.

[0046] Its preparation method comprises the following steps:

[0047] Form a first epitaxial layer on a P-type silicon material substrate with a doping concentration of 1E18 to 1E21, with a layer thickness of 10 to 100um ...

Embodiment 3

[0063] In this embodiment, the conductivity type of the substrate is N-type to illustrate the structure of the above-mentioned power buffer diode chip and its manufacturing method.

[0064] like Figure 6 Shown is a schematic structural diagram of a snubber diode chip using an N-type silicon substrate. The buffer diode chip in the figure includes a silicon substrate doped with N-type impurities, a first epitaxial layer doped with N-type impurities; a second epitaxial layer doped with N-type impurities; a deep diffusion region doped with P-type impurities; The well region with N-type impurities; the shallow diffusion region doped with P-type impurities; and the dielectric layer above the chip; the buffer diode cathode metal layer, that is, the lower metal layer; the anode of the buffer diode is located on the upper metal layer.

[0065] Its preparation method comprises the following steps:

[0066] Form a first epitaxial layer on an N-type silicon material substrate with a do...

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Abstract

The invention discloses a power buffer diode chip structure and a manufacturing method thereof. The power buffer diode chip structure structurally comprises a lower metal layer, a substrate and an epitaxial layer, the lower metal layer, the substrate and the epitaxial layer are laminated from bottom to top in sequence, a deep diffusion area is formed on the epitaxial layer, a well area is formed on the deep diffusion area, a shallow-layer diffusion area is formed on the well area, a channel resistance area is formed on the well area and is connected with the deep diffusion area and the shallow-layer diffusion area, the conducting type of the epitaxial layer and the well area is the same as that of the substrate, and the conducting type of the shallow-layer diffusion area and the deep diffusion area is opposite to that of the substrate; another electrode of a power buffer diode is arranged on the shallow-layer diffusion area, a medium layer is arranged on the connection part of the shallow-layer diffusion area and the resistance area, and metal is arranged on the connection part of the deep diffusion area and the well area. Through the semiconductor structure, multiple components and parts in a circuit are integrated in the same chip, so that the manufactured semiconductor device is small in size, the miniature integration is promoted, and the cost is low.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a power buffer diode chip structure and a manufacturing method thereof. Background technique [0002] Flyback converters used in AC / DC and DC / DC conversion are widely used in low-power power supplies and various power adapters because of their relatively simple circuit structure. In the circuit, due to the influence of parasitic parameters of components, ringing and overshoot will occur at the drain of the switch tube, resulting in increased pressure on the MOS tube and increased loss. Therefore, it is necessary to use a clamp snubber circuit to suppress oscillation and improve Efficiency, the typical method is to use RCD clamp snubber circuit, such as figure 1 shown. [0003] but in such figure 1 In the circuit shown, at the cut-off time of the clamping diode D, due to the influence of the parasitic parameters of the transformer and the field effect transistor, a ringi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/861H01L21/329
CPCH01L29/66136H01L29/861
Inventor 张少锋周仲建
Owner 成都方舟微电子有限公司
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