Method for preparation of graphene electrode MoS2 field effect transistor through thermal reduction

Abstract

The objective of the invention is to provide a method for large-scale preparation of a graphene electrode MoS2 field effect transistor with a high-performance hybrid structure. The method comprises the steps that: MoS2 of CVD growth is directly performed on a SiO2 / Si substrate and MoS2 graphical etching is performed; a thermal scanning probe technology is employed to directly write a size and a shape of a graphene oxide (GO) graph; and the GO is subjected to spin-coating and thermal reduction to obtain a graphene electrode, so that a large-scale graphene electrode MoS2 field effect transistoris formed. The method employs the thermal scanning probe technology to directly write the shape and the size of the spin-coating GO, the GO after thermal reduction is taken as an electrode, so that performances such as contact resistance and a migration rate of the MoS2 field effect transistor are improved. A single layer of MoS2 has many excellent electrical properties such as a large band gap (1.8eV) and a large switch ratio (~108). The graphene electrode can increase charge injection, and can improve the electrical properties of the MoS2 field effect transistor. The graphene electrode MoS2field effect transistor prepared by the invention is simple in technology and good in performance, and can be widely applicable to a large-scale integration logic circuit. Besides, the method has a large market prospect and can prompt commercialization popularization and application.

Description

technical field [0001] The invention relates to a method for large-scale preparation of high-performance MoS2 field-effect transistors in micro-nano electronics manufacturing. Background technique [0002] In the past ten years, the key to the development of digital logic circuits is to manufacture smaller metal-oxide-semiconductor transistors. When the gate length of traditional transistors is less than 10nm, the stability of transistors manufactured by traditional silicon processes will deteriorate (short channel quantum effect), and 10nm will become the limit of silicon-based transistors. Since the discovery of graphene by Geim et al. in 2004, two-dimensional materials with excellent performance have attracted the attention of researchers from all over the world. Single-layer MoS2 has a bandgap of 1.8eV and a switch ratio close to 10 8 , so that it has the potential to be used as a high-performance field effect transistor channel material. Due to the mismatch between t...

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Problems solved by technology

[0004] For the current preparation of high-performance MoS2 field effect transistors, the preparation process is complex and not suitable for large-scale manufacturing.

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