A variable delay asynchronous sequence control circuit and control method

Abstract

The invention provides a variable delay asynchronous time-sequence control circuit and a control method. The VINP differential signal input end and the VINN differential signal input end of the control circuit are respectively connected with a VXP sampling holding circuit and a VXN sampling holding circuit through a sampling switch K1 and a sampling switch K2. The VXP sampling holding circuit is connected with an upper polar plate of a positive N-bit DAC binary capacitor array. The VXN sampling holding circuit is connected with an upper polar plate of a negative N-bit DAC binary capacitor array. The VXP sampling holding circuit and the VXN sampling holding circuit are connected with a comparator. The lower polar plate of the positive N-bit DAC binary capacitor array is connected with a Cparray switch control unit. The lower polar plate of the negative N-bit DAC binary capacitor array is connected with a Cn array switch control unit. The output end of the comparator is connected with an SAR logic control unit. According to the invention, different time delay circuits are adopted between the comparison phase and the capacitor switching phase, so that the unnecessary waiting time ofthe comparator after comparison is reduced.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a variable delay asynchronous sequence control circuit and a control method. Background technique [0002] Analog-to-digital conversion circuits are mainly used in wireless communication, software radio and millimeter wave imaging systems. Among various analog-to-digital conversion circuit structures, the successive approximation type has the advantage of low power consumption. Optimizing the control timing can effectively increase the sampling rate of the successive approximation type analog-to-digital conversion circuit without increasing additional power consumption and complicating the circuit design. Spend. [0003] The control timing of the successive approximation analog-to-digital conversion circuit mainly includes synchronous sequential circuit and asynchronous sequential circuit. The cycle of synchronous timing is determined by the longest comparator time plus the la...

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Problems solved by technology

[0003] The control timing of successive approximation analog-to-digital conversion circuits mainly includes synchronous sequential circuits and asynchronous sequential circuits. The cycle of synchronous timing is determined by the longest comparator time plus the largest capacitor settling time, which will limit the sampling rate of the ADC.

In addition, in the current design of high-speed SAR ADC, if synchronous timing is used, an external clock of gigahertz is required, and the clock jitter of the external clock is required to be small enough, which will greatly increase the difficulty of external clock design

[0004] The asynchronous sequential circuit can effectively solve the problems existing in the synchronous sequential circuit. The asynchronous sequential circuit is divided into a comparison phase and a capacitor switching phase during the conversion process, which correspond to the high and low levels of the asynchronous sequential circuit. For example, under the standard 65nm CMOS process, the comparison time of the comparator in the actual circuit is about 200ps, and the switching time of the capacitor is about 2ns, so there is unnecessary waiting time in the asynchronous timing of the traditional structure

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