Substrate structure and its manufacturing method

Abstract

A substrate structure and its manufacturing method include: a dielectric layer, a metal layer formed on the dielectric layer and having a protrusion, and a protective layer formed on the dielectric layer, the metal layer and the protrusion, and The bonding area and fastening effect between the metal layer and the protection layer are increased by the protrusion, and delamination between the metal layer and the protection layer is avoided.

Description

technical field [0001] The disclosure relates to a substrate structure, in particular to a substrate structure with a metal layer and a manufacturing method thereof. Background technique [0002] With the vigorous development of the electronic industry and the evolution of packaging technology, the size or volume of the semiconductor package is also continuously reduced, and the purpose of making the semiconductor package light, thin and small. The substrates of semiconductor packages currently used in electronic products, such as mobile phone chip carrier boards, lens module circuit boards or coil boards, etc., need to make a large copper area on the surface to achieve the technical effect of heat dissipation or noise reduction, and need Make an insulating protective layer to isolate the circuit and prevent the circuit from contacting other components. [0003] Figure 1A It is a schematic cross-sectional view of a semiconductor package 1 in the prior art. As shown in FIG...

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Problems solved by technology

[0004] However, in the packaging substrate 11, the wiring layers 110, 112 are made of different materials from the insulation protection layer 13, and the materials of the dielectric layer 10 and the insulation protection layer 13 are also different, so the manufacturing of the semiconductor package 1 When a temperature cycle (temperature cycle) or stress change is performed during the process, such as when passing through a reflow furnace, or undergoing a process or test such as dropping, the circuit layer 110, 112 and the insulating protection layer 13 or the dielectric layer 10 and the insulating protection layer The areas where heterogeneous materials are combined between layers 13 are easily separated from each other due to Coefficient of thermal expansion (CTE) mismatch, stress concentration, or poor bonding, that is, delamination occurs. The problems caused by these solder bumps 14 and solder balls 15 cannot be effectively electrically connected to the semiconductor chip 12 and the packaging substrate 11, or the product cannot pass the reliability test, resulting in a poor yield rate of the product

[0005] Also, if Figure 1B As shown, although a roughened structure 110a can be formed on the surface of the wiring layer 110, the Ra value of the roughening degree is about 0.1 to 0.5 microns to increase the bonding between the wiring layer 110 and the insulating protection layer 13, but the wiring The bonding surface between the layer 110 and the insulating protection layer 13 still presents a flat surface, causing the distribution direction of the stress to extend continuously along the bonding surface between the circuit layer 110 and the insulating protection layer 13 (such as Figure 1B The arrow direction A shown, that is, the horizontal direction relative to the surface of the dielectric layer 10), so it is still easy to produce delamination

[0006] In addition, with the packaging requirements of miniaturization of semiconductor packages, the size of the circuit layer 110 is also reduced, making it difficult to perform the roughening process.

What's more, even the roughening process cannot effectively prevent the delamination between the circuit layers 110, 112 and the insulating protection layer 13 or between the dielectric layer 10 and the insulating protection layer 13

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