Metal interconnect structure and method of forming the same

Abstract

The technical scheme of the invention discloses a metal interconnection structure and a forming method thereof. The forming method comprises the steps of providing a substrate layer in which a devicestructure is included; forming a first insulating layer on the substrate layer; forming a touch hole, penetrating the thickness of the first insulating layer, in the first insulating layer, wherein the device structure is exposed by the bottom of the touch hole; forming a conductive layer on the surface of the first insulating layer and in the touch hole, and when the width of slot opening in theconducive layer in the touch hole is one tenth to one eighth of the width of the touch hole, stopping forming the conductive layer technology; forming a second insulating layer on the surface of the conductive layer and in the slot; polishing the second insulating layer and the conductive layer by using polishing solution to expose the first insulating layer, and forming a conductive plug, whereinthe rate of polishing the second insulation layer by the polishing solution is less than the rate of polishing the conductive layer. The metal interconnection structure formed by the method effectivereduces disc type defects, and ensures interconnection performance of metal.

Description

technical field [0001] The invention relates to the manufacturing field of semiconductor devices, in particular to a metal interconnection structure and a forming method thereof. Background technique [0002] With the rapid development of semiconductor device manufacturing technology, semiconductor devices already have deep submicron structures. As the number of devices contained in an integrated circuit continues to increase, the size of the device is also continuously reduced due to the improvement of integration. In order to improve the integration level and reduce the manufacturing cost, the key dimensions of the components are getting smaller and the number of components per unit area of ​​the chip is increasing. The vertical space further increases the integration density of the device. [0003] Currently, during the formation of the metal interconnection structure of semiconductor devices, disc defects are easily generated when the conductive layer is polished, and ...

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Problems solved by technology

[0003] Currently, in the process of forming the metal interconnection structure of semiconductor devices, disc defects are easily generated when the conductive layer is polished, and when the subsequent insulating layer is deposited, the thickness of the insulating layer is relatively thick at the disc defects. After the etching process Causes the residue of the insulating layer, which in turn causes an open circuit and causes the metal interconnection to fail

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