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Method for improving alignment of lithography mark, epitaxial layer for alignment of lithography mark, and preparation method for super-junction

A technology of lithographic marking and epitaxial layer, which is applied in the field of preparation of epitaxial layer and super junction, can solve the problems of difficulty in guaranteeing the quality of epitaxial layer, difficult automatic identification of lithography machine, affecting product production efficiency, etc., and achieves the goal of mark alignment and identification Chance Increase, Integrity Preservation, Performance Improvement Effects

Active Publication Date: 2018-07-31
JILIN SINO MICROELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since the epitaxial growth is a large-area doped growth along the crystal direction on the chip, the overall thickness of the chip increases after each epitaxial growth, and the shape of the lithography mark also changes accordingly, making it difficult for the lithography machine Automatic Identification
[0004] In the early stage of the manufacturing process, the lithographic mark recognition of the lithography machine can be improved by multiple lithography and corrosion methods, but the probability of chip contamination increases during the process of film transfer and film making, and the quality of the subsequent epitaxial layer is difficult. ensure
If this problem occurs in the mass production stage of super junction products, it will occupy the capacity of the production line, increase the cost of the product, and seriously affect the production efficiency of the product

Method used

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  • Method for improving alignment of lithography mark, epitaxial layer for alignment of lithography mark, and preparation method for super-junction
  • Method for improving alignment of lithography mark, epitaxial layer for alignment of lithography mark, and preparation method for super-junction
  • Method for improving alignment of lithography mark, epitaxial layer for alignment of lithography mark, and preparation method for super-junction

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Embodiment Construction

[0025] Embodiments of the present invention will be described in detail below in conjunction with examples, but those skilled in the art will understand that the following examples are only for illustrating the present invention, and should not be considered as limiting the scope of the present invention. Those who do not indicate the specific conditions in the examples are carried out according to the conventional conditions or the conditions suggested by the manufacturer. The reagents or instruments used were not indicated by the manufacturer, and they were all conventional products that could be purchased from the market.

[0026] A method for improving alignment of lithography marks, an epitaxial layer for alignment of lithography marks, and a method for preparing a super junction according to an embodiment of the present invention are described in detail below:

[0027] It is well known that when doping and epitaxial operations are performed on the chip in the radial dire...

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Abstract

The invention discloses a method for improving the alignment of a lithography mark, an epitaxial layer for the alignment of the lithography mark, and a preparation method for a super-junction, and belongs to the field of micro-electronic chips. The method comprises the steps: providing a substrate with an epitaxial layer, wherein the epitaxial layer is provided with a groove which is far from thetop surface far of the substrate and extends inwards from the top surface, the groove is limited by a bottom wall and a side wall, the bottom wall is parallel to the top surface of the epitaxial layer, and the side wall extends towards the epitaxial layer along the top surface; and forming films on a part of the side wall or on the whole side wall. The method facilitates the obtaining of the better and easier alignment effect in the subsequent manufacturing process during lithography marking.

Description

technical field [0001] The invention relates to the field of microelectronic chip production and manufacturing, in particular to a method for improving the alignment of photolithographic marks, an epitaxial layer and a super junction preparation method for photolithographic mark alignment. Background technique [0002] The SuperJunction (super junction) structure in PowerMOSFET (power metal oxide semiconductor field effect transistor) is an innovative structure on the withstand voltage layer. This structure has the characteristics of low on-resistance, high withstand voltage, and low heat generation, and overcomes the "silicon limit" of traditional MOSFETs. [0003] In the manufacturing process of super junction products, a specific well region structure is often achieved through multiple epitaxial growth, photolithography, and implantation steps. Since the epitaxial growth is a large-area doped growth along the crystal direction on the chip, the overall thickness of the ch...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L29/06H01L23/544
CPCH01L23/544H01L29/0634H01L29/66477H01L2223/54426
Inventor 张熠鑫李强杨寿国高宏伟
Owner JILIN SINO MICROELECTRONICS CO LTD
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