Al technical title is built by PatSnap Al team. It summarizes the technical point description of the patent document.
A metallization layer, semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, electric solid-state devices, etc., can solve the problem that the packaging technology cannot meet the requirements of high density, and achieve simple design, simple operation process, and scope of application. wide effect
Inactive Publication Date: 2018-09-04
NO 55 INST CHINA ELECTRONIC SCI & TECHNOLOGYGROUP CO LTD
View PDF3 Cites 0 Cited by
Summary
Abstract
Description
Claims
Application Information
AI Technical Summary
This helps you quickly interpret patents by identifying the three key elements:
Problems solved by technology
Method used
Benefits of technology
Problems solved by technology
[0002] With the miniaturization, light weight, thinning, high performance, increase in the number of I / O ports and the development of functional diversification of electronic products, traditional packaging technology can no longer meet the requirements of high density.
Method used
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more
Image
Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
Click on the blue label to locate the original text in one second.
Reading with bidirectional positioning of images and text.
Smart Image
Examples
Experimental program
Comparison scheme
Effect test
Embodiment 1
[0035] Conduct solder resistance test on 0.45μm 96.5Sn3.0Ag0.5Cu solder balls (96.5, 3.0, 0.5 are percentages):
[0037] (2) Etching the semiconductor substrate by dry method;
[0038] (3) Use PVD (Physical vapor deposition) and electroplating methods to prepare the required insulating layer, adhesion layer, seed layer, solderable layer, barrier layer, protective solderable layer, etc. on the semiconductor surface. In Example 1, the insulating layer, adhesion layer, etc. layer, seed layer, solderable layer, barrier layer, protective solderable layer are SiO 2 , Ti, Au, Cu, Ni, Au;
[0039] (4) After the Au layer of the protective solderable layer pad is coated with glue, the Au in the redundant area is corroded;
[0046] (2) Etching the semiconductor substrate by dry method;
[0047] (3) Prepare the required insulating layer, adhesion layer, seed layer, solderable layer, barrier layer, protective solderable layer, etc. on the surface of the semiconductor by methods such as PVD (Physical vapor deposition) and electroplating. In Example 1, the insulating layer, The adhesion layer, seed layer, solderable layer, barrier layer, and protective solderable layer are SiO 2 , Ti, Au, Cu, Ni, Au;
[0048] (4) After the Au layer of the protective solderable layer pad is coated with glue, the Au in the redundant area is corroded;
[0049] (5) Cr layer of sputtering solder resist layer;
[0051] (7) Solder resistance test was performed with 62Sn36Pb2Ag solder balls in a vac...
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More
PUM
Login to View More
Abstract
The invention relates to a semiconductor metallization layer resistance welding method. The method includes the following steps that: (1) waferadhesivecoating, exposing, developing, and drying are carried out; (2) a semiconductor substrate is etched with dry or wet etching; (3) a required insulating layer, adhesion layer, seed layer, solderable layer, barrier layer and protective solderable layer are prepared on the surface of the semiconductor by means of sputtering, evaporation, PVD (Physical vapor deposition), CVD (Chemical vapor deposition), or electroplating; (4) the protective solderable layer at a redundant region is removed by means of etching; (5) a required solder mask is prepared on the surface of the protective solderable layer by means of sputtering, evaporation, PVD, CVD orelectroplating; (6) an automatic scribing machine is adopted to perform wafer scribing; and (7) solder balls are selected for weldinginterconnection. With the method adopted, the problem of resistance welding between a semiconductor metallization layer and solder balls can be solved, and a practically feasible resistance welding method can be provided for resistance welding between the semiconductor metallization layer and the solder balls. The method has the advantages of simple design, high operability and high applicability.
Description
technical field [0001] The invention relates to a method for resisting soldering of a semiconductor metallization layer, which belongs to the technical fields of micro-interconnect solder joint structure preparation, new material technology and semiconductor devicemanufacturing technology, and provides a method for the connection between the semiconductor metallization layer and solder balls. Practical solder mask method. Background technique [0002] With the miniaturization, light weight, thinning, high performance, increase in the number of I / O ports and the development of functional diversification of electronic products, traditional packaging technology can no longer meet the requirements of high density. The development of two-dimensional and three-dimensional stacking technology has brought hope for high-density packaging. High-density two-dimensional and three-dimensional stacking technologies often use tin-based or indium-based solder balls to achieve electrical i...
Claims
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More
Application Information
Patent Timeline
Application Date:The date an application was filed.
Publication Date:The date a patent or application was officially published.
First Publication Date:The earliest publication date of a patent with the same application number.
Issue Date:Publication date of the patent grant document.
PCT Entry Date:The Entry date of PCT National Phase.
Estimated Expiry Date:The statutory expiry date of a patent right according to the Patent Law, and it is the longest term of protection that the patent right can achieve without the termination of the patent right due to other reasons(Term extension factor has been taken into account ).
Invalid Date:Actual expiry date is based on effective date or publication date of legal transaction data of invalid patent.