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A power device with a surface charge region structure

A surface charge and power device technology, applied in the direction of electrical components, semiconductor devices, circuits, etc., can solve the problems of complex process, high cost and price, and achieve the effect of simple and feasible process, good process tolerance, and prevention of premature breakdown

Active Publication Date: 2021-10-22
GUILIN UNIV OF ELECTRONIC TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The traditional means of improving the withstand voltage are often complicated in process and high in cost and price. The surface charge region structure is adopted, the process is simple and feasible, the process tolerance is good, and it is compatible with the conventional CMOS process

Method used

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  • A power device with a surface charge region structure
  • A power device with a surface charge region structure

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Embodiment 1

[0032] Such as figure 1 The shown power device with a surface charge region structure includes a drift region 5, a substrate II2, a floating equipotential layer 4, and a substrate I1 arranged sequentially from top to bottom; an N+ drain region is arranged on the drift region 5 , drain electrode 10, gate electrode 12, source electrode 11, N+ contact region, P well 7 and P+ source region; the top of the drift region 5 is provided with N + charge region 6, the N + A surface substrate 9 is arranged above the charge region 6; the N + The charge regions 6 are uniformly distributed along the lateral direction. The positions of the gate electrode 12 and the source electrode 11 are lower than the surface substrate 9 .

[0033] Since a series of equidistant N + charge region 6, so the surface charge region is in the adjacent N + The interface charge is generated in the charge interval, which enhances the surface lateral electric field and improves the surface lateral withstand volt...

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Abstract

The invention provides a power device with a surface charge region structure, comprising a P substrate I (1), a floating equipotential layer (4), a P substrate II (2) and a drift region (5) arranged in sequence from bottom to top ); the drift region (5) is provided with an N+ drain region, a drain electrode (10), a gate electrode (12), a source electrode (11), an N+ contact region, a P well (7) and a P+ source region; the A series of N+ charge regions (6) distributed laterally and equidistantly on the top of the drift region (5) and located in the drift region form a surface charge region. The present invention sets a series of equidistant N on the surface of the drift region + The surface charge region structure of the charge region, the surface charge region generates interface charges, which enhances the electric field in the charge region and improves the lateral withstand voltage of the device; the interface charge simultaneously enhances the vertical electric field and vertical withstand voltage of the buried layer, reduces the electric field near the drain, and prevents the device from The surface breaks down prematurely; due to the use of the surface charge region structure with equal spacing N+, the process is simple and feasible, the process tolerance is good, and it is compatible with the conventional CMOS process.

Description

technical field [0001] The invention relates to the technical field of semiconductor power devices, in particular to a power device with a surface charge region structure. Background technique [0002] Power semiconductor devices are semiconductor devices that perform power processing and are the main object of power electronics research. Power electronics was born under the impetus of the development of power semiconductor devices, and has gradually matured after decades of development. Power semiconductor devices have a wide range of applications such as weaponry, power electronics, aerospace, flat panel display drivers and other high-tech industries. However, lateral power devices have lateral channels, and the drain, source, and gate are all on the chip surface, and are easy to integrate with low-voltage signals through internal connections, and are widely used in power integrated circuits. Therefore, experts and scholars at home and abroad have invested great attentio...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/786H01L29/06
CPCH01L29/0623H01L29/78606
Inventor 李琦张昭阳李海鸥陈永和张法碧傅涛鲍婷婷
Owner GUILIN UNIV OF ELECTRONIC TECH
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