Semiconductor structure and formation method thereof

Abstract

A semiconductor structure and a formation method thereof are disclosed. The method comprises the following steps of providing a substrate including an NMOS area; forming a gate structure on the substrate; forming an N-region groove in the substrate of the two sides of the gate structure; forming an N-region doped epitaxial layer in an N-region groove, wherein the N-region doped epitaxial layer isthe laminated structure of a first N-type doped epitaxial layer and a second N-type doped epitaxial layer, the first N-type doped epitaxial layer is a first epitaxial layer doped with N-type ions, thesecond N-type doped epitaxial layer is a second epitaxial layer doped with the N-type ions, and the forbidden band width of the second epitaxial layer is smaller than the forbidden band width of thefirst epitaxial layer; forming an interlayer dielectric layer on the N-region doped epitaxial layer; forming a first contact opening which is exposed out of the N-region doped epitaxial layer in the interlayer dielectric layer; and forming a first contact hole plug in the first contact opening. In the invention, through the second epitaxial layer doped with the N-type ions, a Schottky barrier height is reduced, the N-type ion concentration of the N-region doped epitaxial layer is increased and a contact resistance is reduced.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] With the continuous development of integrated circuit manufacturing technology, people's requirements for the integration and performance of integrated circuits are becoming higher and higher. In order to improve integration and reduce costs, the critical dimensions of components are getting smaller and the circuit density inside integrated circuits is increasing. This development makes the surface of the wafer unable to provide enough area to make the required interconnection lines. [0003] In order to meet the requirements of the interconnection line after the critical dimension is reduced, at present, the conduction between different metal layers or between the metal layer and the substrate is realized through the interconnection structure. The interconnection structure includes interconnectio...

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Problems solved by technology

[0006] However, the electrical performance of the formed semiconductor structur

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