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Semiconductor device and manufacturing method thereof and electronic device

An electronic device and semiconductor technology, which is applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve problems such as the impact of breakdown performance, the reduction of dielectric spacing, and the impact on device performance and yield.

Active Publication Date: 2018-11-02
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to the continuous advancement of technology nodes, the feature size of devices continues to shrink, and the critical size of the bit line and the sheet resistance (Rs) of the bit line are limited. In order to reduce the sheet resistance (Rs), copper is usually selected as the metal of the bit line. In order to obtain Better copper filling performance, usually an inverted trapezoidal shape, further reduces the dielectric spacing between adjacent bit lines, thus affecting the breakdown performance between bit lines, which in turn affects device performance and yield

Method used

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  • Semiconductor device and manufacturing method thereof and electronic device
  • Semiconductor device and manufacturing method thereof and electronic device
  • Semiconductor device and manufacturing method thereof and electronic device

Examples

Experimental program
Comparison scheme
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Embodiment 1

[0081] The invention provides a semiconductor device, such as Figures 3A-3C As shown, the semiconductor device includes:

[0082] a bit line arranged along the first direction, the bit line is electrically connected to the device below it;

[0083] Wherein, the bit lines include a first bit line 305 and a second bit line 307 arranged vertically and staggeredly, and the first bit line 305 and the second bit line 307 are arranged in the first direction perpendicular to the first direction. Alternately set in two directions.

[0084] Specifically, the staggered arrangement and alternate arrangement between the first bit line and the second bit line means that the interval between two adjacent first bit lines corresponds to the upper and lower sides of the second bit line, and the interval between two adjacent first bit lines corresponds up and down. The interval between the two bit lines corresponds to the upper and lower sides of the first bit line.

[0085] Among them, such...

Embodiment 2

[0122] Hereinafter, detailed steps of an exemplary method of a method for manufacturing a semiconductor device proposed by an embodiment of the present invention will be described with reference to the accompanying drawings. in, Figures 4A-4F It is a cross-sectional view along the direction of the word line during the preparation process of the bit line in the semiconductor device described in the present invention; Figure 5 It is a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0123] Figure 5 It is a schematic flowchart of a method for manufacturing a semiconductor device according to another embodiment of the present invention, specifically including:

[0124] Step S1: forming a bit line in a first direction, the bit line is electrically connected to the device below it; wherein, the bit line includes a first bit line and a second bit line arranged up and down alternately, and the first bi...

Embodiment 3

[0175] The present invention also provides an electronic device, including the semiconductor device described in Embodiment 1. Wherein, the semiconductor device is the semiconductor device described in Embodiment 1, or the semiconductor device obtained according to the preparation method described in Embodiment 2.

[0176] The electronic device of this embodiment can be any electronic device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a TV set, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, MP3, MP4, PSP, etc. Product or equipment, but also any intermediate product including electrical circuits. The electronic device according to the embodiment of the present invention has better performance due to the use of the above-mentioned semiconductor device.

[0177] in, Figure 6 An example of a mobile phone handset is shown. The mobile phone handset 400 is provided with a display portion ...

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PUM

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Abstract

The invention relates to a semiconductor device and a manufacturing method thereof and an electronic device. The semiconductor device comprises bit lines arranged along a first direction, wherein thebit lines are electrically connected with devices at the lower parts of the bit lines; the bit lines include first bit lines and second bit lines which are arranged in an up-and-down staggered manner;and the first bit lines and the second bit lines are alternately arranged in a second direction vertical to the first direction. The breakdown problem caused by reduction of dielectric spaces betweenthe bit lines due to size reduction can be avoided through the arrangement; the spaces between the adjacent bit lines on the same layer can be increased through up-and-down staggered arrangement, andthe problem that the spaces are too small due to the fact that the adjacent bit lines are located on different layers is avoided, so that the performance and the yield of the device can be further improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a preparation method thereof, and an electronic device. Background technique [0002] For the increasing demand for high-capacity semiconductor storage devices, the integration density of these semiconductor storage devices has attracted people's attention. In order to increase the integration density of semiconductor storage devices, many different methods have been adopted in the prior art, such as by reducing the wafer size. And / or change the internal structure unit to form multiple memory units on a single wafer. For the method of increasing the integration density by changing the unit structure, attempts have been made to reduce the size of the unit by changing the planar layout of the active region or changing the cell layout. area. [0003] With the continuous shrinking of the size of semiconductor devices, the bit line process has been grea...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/528H01L21/768
CPCH01L21/76838H01L23/528
Inventor 张永兴杨海玩李晓波
Owner SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP