An electric leakage process automatic control dynamic random access memory cell with SOI structure

Abstract

The invention relates to an electric leakage process automatic control dynamic random access memory (DRAM) cell with an SOI (Silicon on Insulator) structure. The structure mainly includes an array access transistor, a storage capacitor, and an insulating layer that isolates them. The bottom electrode of the storage capacitor extends to below an array access transistor channel and is connected to the source of the transistor through the insulating layer. Compared with the prior art, the invention utilizes the expanded capacitor control transistor channel, can realize the self-control of the sub-threshold electric leakage channel of a storage capacitor in the off-state electric leakage process, further reduces the leakage current, and thus improves the retention time of charges on the storage capacitor.

Description

technical field [0001] The present invention relates to the structural design of the DRAM, in particular to the off-state leakage control method of the storage capacitor of the DRAM, especially after changing the electrode structure of the storage capacitor, using the potential on the storage capacitor to control the channel of the access transistor to improve the The leakage of the storage capacitor itself on the sub-threshold leakage path is prevented, the self-control of the leakage process is realized, and the charge storage time on the storage capacitor is improved, that is, the data retention time. Background technique [0002] Dynamic random access memory (DRAM) is a widely used semiconductor memory, which accounts for about 10% of the global semiconductor integrated circuit market share, exceeding 30 billion US dollars per year, and plays an irreplaceable role in communications, computers, servers, etc. The core storage unit of a DRAM device is simple, consisting of ...

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Problems solved by technology

[0005] However, with the continuous increase of integration, the size of DRAM memory cells will continue to shrink to less than 20nm, and the access transistor will also be further reduced. The recessed channel has limited control over the off-state leakage current of the access transistor. It is very difficult to achieve the data retention time requirement of

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