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SiC-groove MOS device and fabrication method thereof

A technology of a MOS device and a manufacturing method, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of aggravated ion scattering and low channel electron mobility of SiC trench power MOS devices, and achieves improvement. The effect of low carrier mobility, reduced probability of carrier collision or scattering, and improved electrical conductivity

Inactive Publication Date: 2019-03-01
QINHUANGDAO JINGHE SCI & TECH RES INST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This high surface roughness makes the ion collision of carriers through the inversion channel layer more obvious when the device is working, and the ion scattering phenomenon is intensified, resulting in extremely low channel electron mobility of SiC trench power MOS devices.

Method used

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  • SiC-groove MOS device and fabrication method thereof
  • SiC-groove MOS device and fabrication method thereof
  • SiC-groove MOS device and fabrication method thereof

Examples

Experimental program
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Embodiment 1

[0036] See figure 1 , figure 1 A schematic structural diagram of a SiC trench MOS device provided for an embodiment of the present invention; it includes a drain 9, a SiC substrate layer 8, an N-type doped epitaxial layer 7, a P-type doped Epitaxial layer 6, N-type doped epitaxial layer 5; P-type doped epitaxial layer 3, arranged in the middle of the N-type doped epitaxial layer 5 and the P-type doped epitaxial layer 6, and extending to the N-type The doped epitaxial layer 7 extends to a depth not exceeding half of the thickness of the N-type doped epitaxial layer 7; wherein, both sides of the P-type doped epitaxial layer 3 extend to part of the N-type doped epitaxial layer 5; SiO 2 The gate oxide layer 2 is arranged on the P-type doped epitaxial layer 3; the gate 1 is arranged on the SiO 2 On the gate oxide layer 2 ; the source electrode 4 is arranged in partial regions on both sides of the N-type doped epitaxial layer 5 .

[0037] Specifically, the material of the drain e...

Embodiment 2

[0041] See image 3 , image 3 A schematic diagram of the preparation process of a method for preparing a SiC trench MOS device provided in an embodiment of the present invention; please refer to Figure 4a-Figure 4h , Figure 4a-Figure 4h A schematic diagram of the manufacturing steps of a method for manufacturing a SiC trench MOS device provided by the embodiment of the present invention; this embodiment focuses on the detailed description of the method for manufacturing a SiC trench MOS device on the basis of the above-mentioned embodiments.

[0042] Specifically, the fabrication method of the SiC trench MOS device is as follows:

[0043] Step 1. Epitaxial N-epitaxial layer:

[0044] Such as Figure 4a As shown, the thickness of the epitaxial growth on the SiC substrate layer 8 is 5-35 μm, and the doping concentration is 1×10 15 cm -3 ~1×10 16 cm -3 N-epitaxial layer 7.

[0045] Step 2. Epitaxial P+ epitaxial layer:

[0046] Such as Figure 4b As shown, the epita...

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Abstract

The invention relates to a SiC-groove MOS device and a fabrication method thereof. The SiC-groove MOS device comprises a drain, a SiC substrate layer, an N-type doping epitaxial layer, a P-type dopingepitaxial layer and an N-type doping epitaxial layer which are sequentially laminated from bottom to top, wherein the P-type doping epitaxial layer is arranged between the N-type doping epitaxial layer and the P-type doping epitaxial layer and extends to the N-type doping epitaxial layer, the extension depth does not exceed the thickness of the N-type doping epitaxial layer by half, two sides ofthe P-type doping epitaxial layer extend to a part of the N-type doping epitaxial layer, a SiO2 gate oxide layer is arranged on the P-type doping epitaxial layer, a gate is arranged on the SiO2 gate oxide layer, and a source is arranged at a part of region at two sides of an N-type heavy-doping epitaxial layer. With the SiC-groove MOS device provided by the embodiment of the invention, the carriercollision or scattering probability in a conductive channel is reduced, the problem of low carrier mobility of an inverse channel of a SiC MOSFET is improved, and the conductivity of the device is improved.

Description

technical field [0001] The invention relates to the field of semiconductor devices, in particular to a SiC trench MOS device and a manufacturing method thereof. Background technique [0002] Wide bandgap semiconductor materials are the third generation of semiconductors developed after the first generation of silicon, germanium and the second generation of gallium arsenide, indium phosphide and other materials. Among the third-generation semiconductor materials, silicon carbide (SiC) and gallium nitride (GaN) are among the best. SiC material technology is mature, and there are already high-quality 4-inch wafers. However, gallium nitride materials do not have a gallium nitride substrate, and epitaxy can only rely on other materials. Its thermal conductivity is only a quarter of that of SiC, and P-type doping cannot be achieved. This limits the application of gallium nitride materials in high voltage and high power. In comparison, the advantages of SiC materials in the field...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/786H01L29/06H01L21/336
CPCH01L29/0684H01L29/66068H01L29/78606H01L29/78642H01L29/78696
Inventor 邵锦文侯同晓孙致祥贾仁需元磊张秋洁刘学松
Owner QINHUANGDAO JINGHE SCI & TECH RES INST CO LTD