Silicon-based integrated on-chip multimode optical switching system compatible with wavelength division multiplexing signals

Abstract

A silicon-based integrated on-chip multimode optical switching system compatible with wavelength division multiplexing signals comprises a multimode optical switching array, N groups of wavelength division-mode division multiplexing optical signal transmitting and receiving systems, and a peripheral driving circuit system, an electrical serial-parallel conversion and parallel-serial conversion system and a high-speed data input and output electrical bus which are used for supporting the system on the chip. According to the system, high-speed serial electric signals generated by data processing nodes are converted into parallel multi-channel electric signals to be input; the optical signal is converted into an optical signal through a modulator array and is loaded on an optical carrier wave of which the wavelength and the mode are multiplexed together; the optical signals enter the multi-mode optical switching array through the multi-mode waveguide input port, are demultiplexed into optical signals of multiple channels after reaching the target port, are converted into parallel electric signals through the photoelectric detector, and are finally reduced into high-speed serial signals to be provided for a data node of the target port for use. The system has the characteristics of low energy consumption, high bandwidth and low delay. The data input interface and the data output interface are both electric domains and are compatible with data interfaces of various existing processors.

Description

technical field [0001] The invention relates to the technical field of on-chip optical interconnection and integrated optics, in particular to a silicon-based integrated on-chip multi-mode optical switching system compatible with wavelength division multiplexing signals. Background technique [0002] In recent years, the method of improving processor performance by increasing the main frequency has encountered the limitation of power consumption. The architecture of multi-core parallel processing has become an important means for continuous improvement of processor performance. The overall performance of a multi-core processor is not only related to the number and performance of the processing cores, but also depends on the communication efficiency between the processing cores. A multi-core processor uses an on-chip network constructed of metal wires to exchange information between processing cores. As more and more processing cores are integrated on a chip, the requiremen...

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Problems solved by technology

As more and more processing cores are integrated on a chip, the requirements for the communication bandwidth of the on-chip network are getting higher and higher. The on-chip network implemented by traditional metal wiring has become a constraint for multi-core processing due to its high power consumption, low bandwidth and high delay. a bottleneck in the development of

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