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Semiconductor device and method of forming the same

A semiconductor and device technology, applied in the field of semiconductor devices and their formation, can solve problems such as poor performance of semiconductor devices, and achieve the effects of life extension, time extension, and enhanced reliability

Active Publication Date: 2022-05-13
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, the performance of semiconductor devices formed by existing methods for forming semiconductor devices is poor

Method used

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  • Semiconductor device and method of forming the same
  • Semiconductor device and method of forming the same
  • Semiconductor device and method of forming the same

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Embodiment Construction

[0030] As mentioned in the background, semiconductor devices formed in the prior art have poor performance.

[0031] A method for forming a semiconductor device, comprising: providing a substrate 100 with a fin 110 and an isolation structure 101 on the substrate 100; forming a dummy gate structure on the fin 110; forming a dummy gate structure in the fins 101 on both sides of the dummy gate structure The source-drain doped layer 150; after the source-drain doped layer 150 is formed, a dielectric layer 170 covering the sidewall of the dummy gate structure is formed on the substrate 100; after the dielectric layer 170 is formed, the dummy gate structure is removed, and the dummy gate structure is formed in the dielectric layer Gate opening; form an interface layer 121 at the bottom of the gate opening; form a gate dielectric layer 122 on the sidewall and interface layer of the gate opening; after forming the gate dielectric layer 122, form a work function layer 123 and a gate ele...

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Abstract

A semiconductor device and a method for forming the same, the method comprising: providing a substrate, the substrate has a first region, the substrate has a first fin and a first dummy gate structure, and the first dummy gate structure includes a first dummy gate layer; Form a dielectric layer covering the sidewall surface of the first dummy gate structure on the substrate; remove the first dummy gate layer, and form a first gate opening in the dielectric layer; form an interface layer at the bottom of the first gate opening; The sidewall and bottom of the opening form a gate dielectric layer on the interface layer; a sacrificial layer is formed on the gate dielectric layer, the top surface of the sacrificial layer is lower than the top surface of the first fin, and the sacrificial layer exposes the top and part of the side of the first fin The gate dielectric layer on the wall surface; the interface layer under the gate dielectric layer exposed by the sacrificial layer is annealed to increase the thickness of the interface layer not covered by the sacrificial layer; the sacrificial layer is finally removed; and then formed on the surface of the gate dielectric layer The gate electrode layer filling the first gate opening. The method improves the performance of semiconductor devices.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a forming method thereof. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher element density and higher integration. As the most basic semiconductor device, the device is being widely used at present. The control ability of the traditional planar device to the channel current is weakened, resulting in the short channel effect and causing the leakage current, which ultimately affects the electrical performance of the semiconductor device. [0003] In order to overcome the short channel effect of the device and suppress the leakage current, the prior art proposes a fin field effect transistor (Fin FET), which is a common multi-gate device, and the structure of the fin field effect transistor includes : the fin and the isolation layer located on the...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/8234
CPCH01L29/66787H01L29/66545H01L21/823431
Inventor 周飞
Owner SEMICON MFG INT (SHANGHAI) CORP
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