Preparation method of power semiconductor device
A technology of power semiconductors and semiconductors, which is applied in the manufacture of semiconductors/solid-state devices, electrical components, circuits, etc., can solve problems such as needs, and achieve the effects of reducing manufacturing costs, simplifying the process, and reducing the area
Active Publication Date: 2019-08-30
爱特微(张家港)半导体技术有限公司
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Problems solved by technology
[0008] The present invention aims to solve the problem that additional dopant ion implantation and diffusion processing are required in order to form the edge terminal structure in the above-mentioned semiconductor device, omits additional dopant ion implantation and diffusion processes when forming the edge terminal, and provides a method that simplifies the process. Manufacturing method of power semiconductor device while reducing manufacturing cost
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Embodiment 1
[0027] Figure 1 to Figure 9 It is a cross-sectional view of a MOSFET power semiconductor device for N channel (N channel) electric power prepared by the method of the invention.
[0028] Step ① "Grow a layer of thermal oxide film (103) on the front surface of the first conductivity type semiconductor substrate (101) that has been divided into the active region (A) and the edge termination region (B), and the active region (A) ) and the thermal oxide film (103) on the edge terminal region (B) is selectively removed" The preparation process is as follows:
[0029] Such as figure 1As shown, a layer of phosphorus (phosphorus) doped epitaxial layer (102) is grown on a semiconductor substrate (101) of an antimony (Sb) substrate; the semiconductor substrate (101) containing the epitaxial layer (102) is Perform thermal oxidation processing at a temperature of 900-1200° C., and grow a layer with a thickness of thermally oxidized film (103); apply photoresist (104) for the first...
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The invention relates to a preparation method of a power semiconductor device. When the power semiconductor device is prepared, an edge terminal area must be formed around the power semiconductor device in order to support the high voltage connection of the anode and the cathode during turn-off of the device. The basic constitutive elements include that the additional mask layer step and ion implantation step are not required to be performed in the processing process of forming a P-type well or an N-type well of a PN junction, the processing process is simultaneously conducted with the ion implantation step required by the formation of most MOS gate structure cells or diode cells in an active region, and wells with the same concentration are formed due to the simultaneous ion implantation.
Description
technical field [0001] The invention relates to the field of power semiconductors, in particular to a method for preparing a power semiconductor device which can simplify the process and reduce the preparation cost at the same time. Background technique [0002] According to the trend of increasing the size and capacity of applied machines recently, the demand for power semiconductor devices with high breakdown voltage, high current and fast switching characteristics has increased rapidly, especially in order to reduce the current Power loss due to excessive power requires power semiconductor devices with low on-resistance and low saturation voltage. [0003] In addition, in the off state or the moment the switch is turned off, it needs to be able to support the high voltage applied across the power semiconductor device in the opposite direction to the PN junction, that is, it needs to have high breakdown voltage characteristics; on the other hand, the breakdown voltage of t...
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IPC IPC(8): H01L21/8234H01L21/425
CPCH01L21/425H01L21/823418H01L21/823437H01L21/823475
Inventor 金恩泽李宗宪尹锺晚
Owner 爱特微(张家港)半导体技术有限公司