Low-power-consumption ultra-high-speed high-precision analog-to-digital converter

Abstract

The invention discloses a low-power-consumption ultra-high-speed high-precision analog-to-digital converter. The analog-to-digital converter comprises an input circuit, a low-speed ADC, a 1 / 16 frequency divider and an output circuit, the input circuit is connected with the low-speed ADC, the low-speed ADC is connected with the output circuit, and the 1 / 16 frequency divider is connected with the input circuit and the low-speed ADC; the input circuit samples an input signal by adopting the frequency of 1.6 GHz. The low-speed ADC is used for acquiring signals from the input circuit at the frequency of 100MHz; the low-power-consumption ADC circuit architecture with the 10-bit resolution gigahertz sampling frequency is constructed in an IC chip.

Description

technical field

[0001] The invention relates to the technical field of analog-to-digital conversion, in particular to an ultra-high-speed and high-precision analog-to-digital converter with low power consumption. Background technique

[0002] With the continuous increase in the bandwidth requirements of input analog signals and the increase in the demand for direct sampling of radio frequency signals, there is a huge market demand for ultra-high-speed analog-to-digital converter (ADC) chips.

[0003] The existing ultra-high-speed ADC architectures mainly include Flash, folding interpolation, Pipeline, and time interleaving.

[0004] Flash ADC, also known as parallel ADC, is the simplest ADC architecture in the industry that can achieve the highest conversion rate. However, as the resolution increases, the number of comparators required increases exponentially, resulting in chip Significant increase in area and power consumption. In addition, the offset mismatch between the...

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