Anufacturing method of self-aligned quadruple pattern and manufacturing method of semiconductor device

Abstract

The invention relates to a manufacturing method of a self-aligned quadruple pattern. The manufacturing method comprises: sequentially forming a second core mold layer, a second anti-reflection layer,a first core mold layer and a first anti-reflection layer on a target etching layer; etching the first anti-reflection layer and the first core mold layer to form a first core mold pattern; covering the first core mold pattern with a first side wall material layer; etching the first side wall material layer and the first core mold pattern to form a first side wall; etching part of the thickness ofthe second anti-reflection layer by taking the first side wall as a mask, and forming a groove in an exposed area of the second anti-reflection layer; etching the second anti-reflection layer and thesecond core mold layer to form a second core mold pattern; covering a second side wall material layer on the second core mold pattern; and etching the second side wall material layer and the second core mold pattern to form a second side wall located on the target etching layer. According to the manufacturing method, the line edge roughness and the line width roughness of the semiconductor devicecan be improved.

Description

Technical field [0001] The present invention relates to the field of manufacturing integrated circuits, and in particular to a method for manufacturing a self-aligned quadruple pattern and a method for manufacturing a semiconductor device. Background technique [0002] In the field of integrated circuits, lithography (Lithography) technology is a core part of IC manufacturing, and its main function is to transfer the chip circuit pattern on the mask to the silicon wafer. The photolithography process defines the size of the semiconductor device. Current semiconductor devices have increasingly smaller requirements for critical dimensions. For example, the channel length of field effect transistors has reached the deep sub-micron range. The smaller the feature size, the higher the integration of the chip, the better the performance, and the lower the power consumption. However, as the size shrinks, the influence of the photoresist exposure process on the line edge roughness (LER) ...

AI Technical Summary

Problems solved by technology

However, these technologies are costly

Moreover, 193nm immersion lithography technology cannot realize the process node of 14nm and below

Although EUV lithography technology can achieve smaller process nodes, EUV photoresist still faces great difficulties and challenges in terms of resolution, line edge roughness and sensitivity, and has not yet achieved mass production capacity.

Images