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Wafer cleaning method and semiconductor device manufacturing method

A technology for semiconductors and wafers, applied in the field of wafer cleaning methods and semiconductor device manufacturing, can solve the problems of large residues, high costs, and long process cycles, and achieve the effects of simplifying the deglue process, improving the effect, and shortening the process cycle

Active Publication Date: 2022-03-29
CHANGXIN MEMORY TECH INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] At present, the most common method of the existing lithography stripping and reworking process is to first dry ashing and then wet chemical stripping, and different types / combinations of lithography masking layers will be selected. In the reworkflow, there are many kinds of chemical reagents used and the treatment chamber needs to be transferred, that is, these reworkflows are all in a variety of multi-step ways, the process cycle time is long, the cost is high, and Some of the degumming processes have more residues after degumming, which leads to the need for repeated photolithography rework several times in the follow-up, and the process cycle becomes longer

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  • Wafer cleaning method and semiconductor device manufacturing method
  • Wafer cleaning method and semiconductor device manufacturing method
  • Wafer cleaning method and semiconductor device manufacturing method

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Embodiment Construction

[0037] The inventors found that there are three types of photolithographic masking layers that usually need to be removed: the first type of photolithographic masking layer includes an anti-reflection layer 101 (mainly composed of Si, C, H, O) and Photoresist layer 102 (mainly composed of C, H, O), such as Figure 1A As shown; the second type of photolithographic masking layer includes an anti-reflection layer 101 stacked on the wafer 100, such as Figure 1B As shown; the third type of photolithographic masking layer includes a spin-on-carbon layer 103 (mainly composed of C, H, and O), an anti-reflection layer 101 and a photoresist layer 102 stacked on the wafer 100 in sequence.

[0038] for Figure 1A The first type of photolithographic masking layer shown and Figure 1B For the second type of photolithographic masking layer shown, the existing stripping and rework process is as follows: Please refer to Figure 1A-1B and Figure 2A , first of all, using high-power, high-f...

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Abstract

The invention provides a method for cleaning a wafer and a method for manufacturing a semiconductor device. In the same cleaning tank, the surface of the wafer is first cleaned with a pickling mixed solution to remove most of the surface of the wafer. Photolithographic masking layer, only some residues remain, and then the surface of the wafer is cleaned for the second time with a rinse mixed solution to remove the residues, thus, the existing multiple cleaning methods can be replaced by one-step cleaning. The multi-step cleaning method simplifies the degumming process, reduces costs, shortens the process cycle, and avoids degumming residue. In addition, there is a liquid change flushing time between the two cleanings, and the liquid changing flushing time is shorter than the first cleaning time and longer than the second cleaning time, so as to improve the effect of the second cleaning. The technical scheme of the invention is applicable to various processes requiring photolithography masks, such as hard mask layer etching, ion implantation, gate etching, contact hole etching, and metal interconnection layers.

Description

technical field [0001] The invention relates to the technical field of semiconductor production and manufacturing, in particular to a wafer cleaning method and a semiconductor device manufacturing method. Background technique [0002] Photolithography technology is a process technology that uses optical-chemical reaction principles and chemical and physical etching methods in integrated circuit manufacturing to transfer circuit graphics to the surface of semiconductor wafers or dielectric layers to form effective graphics windows or functional graphics. With the development of semiconductor technology, the critical dimension of the pattern transferred by lithography technology is gradually reduced, and the requirements for pattern accuracy, uniformity and registration accuracy are becoming more and more stringent. It is around 3% to 10%. When the photolithographic dimensional accuracy, registration accuracy or photoresist topography exceed the allowable range, the semicondu...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/02
CPCH01L21/02057H01L21/02082
Inventor 章杏
Owner CHANGXIN MEMORY TECH INC