High-reliability image sensor wafer-level fan-out packaging structure and method

Abstract

The invention provides a high-reliability image sensor wafer-level fan-out packaging structure and method. The high-reliability image sensor wafer-level fan-out packaging structure comprises a substrate, a CIS chip, and solder balls. A photosensitive area of the CIS chip is arranged facing one surface of the substrate and the CIS chip is connected with one surface of the substrate through an areaaround the photosensitive area, a gap at the welding position of the CIS chip and the substrate is sealed through a light shielding material, and a back surface and a side surface of the CIS chip aresubjected to integral plastic package through a plastic package layer; the solder balls are arranged on a surface of the plastic package layer, and an RDL layer of the substrate is fanned out to the surface of the plastic package layer through through holes formed in the plastic package layer and is connected with the solder balls. According to the high-reliability image sensor wafer-level fan-outpackaging structure, the problem that RDL wiring cannot be achieved due to the fact that the size of a chip is miniaturized but functions are integrated in wafer-level packaging is solved, and the problems that a traditional substrate fan-out process is high in cost and low in yield can be solved.

Description

[0001] This application claims the priority of China's earlier application, application number 2019113029655, application date 2019-12-17, and the disclosure of this patent application is incorporated herein by reference in its entirety. Technical field [0002] The invention relates to the technical field of semiconductor chips, in particular to a high-reliability image sensor wafer-level fan-out packaging structure and method. Background technique [0003] The photosensitive chip (CIS chip) is an electronic device that can sense external light and convert it into electrical signals, which is used in electronic equipment such as digital cameras and digital video cameras. The photosensitive chip is usually manufactured by a semiconductor manufacturing process, and then a series of packaging processes are performed on the photosensitive chip to form a packaged package structure. [0004] In the prior art, the fan-out package structure of the photosensitive chip mainly includes a fan-...

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Problems solved by technology

[0006] (1) The thickness of the CIS chip is limited by the height of the solder balls. In order to meet the requirements of solder ball soldering in the later stage, the thickness of the CIS chip is required to be smaller than the height of the solder balls. However, if the chip thickness is too thin, it will easily cause chip cracks and other failures;

[0007] (2) The pad signal of the CIS chip is fanned out to the surrounding edge area, but the center area cannot be equipped with RDL on the glass cover of the photosensitive area, so the signal fan-out area is limited, which is not suitable for high I / O chip packaging;

[0008] (3) There is no protective measure after the CIS chip is thinned, and the reliability of the overall packaging structure is poor. If it is used in a harsh environment, it is necessary to put forward higher requirements for the sensitivity, reliability, and durability of the chip;

[0009] (4) This packaging technology is non-wafer-level packaging, and compared with wafer-level packaging, the cost is higher

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