Quantum well structure and growth method thereof

A growth method and quantum well technology, which is applied in the field of semiconductor materials, can solve problems affecting film deposition, reduce In incorporation rate, and a large number of In vacancies, so as to improve growth quality, optimize growth temperature, and improve crystal quality and optical properties. Effect

Active Publication Date: 2020-07-24
CHANGCHUN UNIV OF SCI & TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

High temperature conditions are not suitable for the deposition of InGaAs materials, resulting in the desorption and evaporation of In atoms, which greatly reduces the incorporation rate of In. On the one hand, the loss of In components

Method used

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  • Quantum well structure and growth method thereof
  • Quantum well structure and growth method thereof
  • Quantum well structure and growth method thereof

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Experimental program
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Effect test

Embodiment 1

[0072] In this embodiment, the InGaAs / GaAs quantum well structure is grown by MOCVD equipment, wherein the GaAs lower barrier layer growth temperature T 1 is 650℃, and the potential well layer is In 0.25 GaAs, the thickness is 8nm, the growth temperature is T 2 It is 540°C. The growth temperature of the GaAs upper barrier layer is the same as 540°C, and the thickness is 20nm, that is, in this embodiment, the GaAs upper barrier layer is not grown at a variable temperature, but isothermally grown, T 2 =T 3 = 540°C. figure 2 It is the atomic force microscope test result of the surface of the barrier layer on the isothermally grown GaAs, the surface roughness is 0.143nm, the surface step spacing is small, about 32nm, and there are many small two-dimensional islands distributed on these mesas, indicating that the two-dimensional Layered growth mode and step flow growth mode coexist. However, the step-flow growth mode is the best growth mode to obtain a complete lattice struct...

Embodiment 2

[0074] In this embodiment, the InGaAs / GaAs quantum well structure is grown by MOCVD equipment, wherein the GaAs lower barrier layer growth temperature T 1 is 650℃, and the potential well layer is In 0.25 GaAs, growth temperature T 2 is 540°C, the growth temperature of the GaAs low-temperature barrier layer is also 540°C, and the thickness h 1 2nm, GaAs high temperature barrier layer growth temperature T 3 650°C, thickness h 2 18nm. image 3 The atomic force microscope test results of the surface of the barrier layer on GaAs grown at variable temperature, the surface roughness is 0.128nm, the surface step spacing is wide, about 49nm, and there are only a few two-dimensional islands on the step surface, and the size is relatively large, indicating that the large Most atoms choose the step flow growth mode, and very few choose the two-dimensional layered growth mode. It can be seen that temperature affects the choice of atoms for nucleation sites. From a thermodynamic point...

Embodiment 3

[0076] In this embodiment, the InGaAs / GaAs quantum well structure is grown by MOCVD equipment, wherein the GaAs lower barrier layer growth temperature T 1 is 650℃, and the potential well layer is In 0.25 GaAs, growth temperature T 2 is 560°C, the growth temperature of the GaAs low-temperature barrier layer is also 560°C, and the thickness h 1 2nm, GaAs high temperature barrier layer growth temperature T 3 650°C, thickness h 2 18nm. Image 6 The atomic force microscope test results of the surface of the barrier layer on the variable temperature grown GaAs show that the surface steps are equidistant, with an interval of about 30nm, and there are no two-dimensional islands, indicating that it has completely transformed into a step flow growth mode at this time. Figure 5It is the X-ray diffraction test result of the InGaAs / GaAs quantum well structure, and interference fringes appear in the diffraction peak of InGaAs, indicating that the crystalline quality of the InGaAs poten...

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Abstract

The invention belongs to the technical field of semiconductor materials, and particularly relates to a quantum well structure and a growth method thereof. In order to obtain a high-quality InGaAs quantum well, a GaAsP strain compensation barrier layer method is generally adopted, but an expected light-emitting peak is caused. Even if the total strain is kept to be zero, InGaAs/GaAsP interface roughening can still be caused, local microdefects can be caused, and the performance of the quantum well can be weakened. If GaAs is directly used as a barrier layer, the selection of the growth temperature is challenging. The quantum well structure provided by the invention comprises a substrate, a buffer layer, a lower barrier layer, a potential well layer and an upper barrier layer which are stacked in sequence. The upper barrier layer comprises a low-temperature barrier layer and a high-temperature barrier layer. The potential well layer, the low-temperature barrier layer and the high-temperature barrier layer are stacked in sequence. The thickness distribution and growth temperature of the low-temperature and high-temperature barrier layers are optimized, and the growth quality of the quantum well material is improved.

Description

technical field [0001] The application belongs to the technical field of semiconductor materials, and in particular relates to a quantum well structure and a growth method thereof. Background technique [0002] A quantum well refers to a potential well on a microscopic scale comparable to the De Broglie wavelength of an electron. The basic characteristic of the quantum well is that due to the limitation of the width of the quantum well (a scale comparable to the De Broglie wavelength of the electron), the localization of the carrier wave function in the one-dimensional direction is caused. In the quantum well, because the active layer The thickness is only within the mean free path of electrons, and the well wall has a strong confinement effect, so that the carriers only have two-dimensional degrees of freedom in the plane parallel to the well wall, and in the vertical direction, the conduction band and valence band are split into subbands . The electronic states, phonon s...

Claims

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Application Information

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IPC IPC(8): H01L31/0352H01L31/0304H01L31/18
CPCH01L31/03046H01L31/035209H01L31/035236H01L31/18H01L31/1876Y02P70/50
Inventor 王海珠王曲惠范杰邹永刚马晓辉石琳琳
Owner CHANGCHUN UNIV OF SCI & TECH
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