Pixel-level high-speed narrow-pulse peak holding circuit

A peak hold circuit and narrow pulse technology, which is applied in pulse processing, pulse technology, electrical components, etc., can solve the problems of large power consumption and large area, and achieve the effects of low power consumption, high holding accuracy, and small occupied area

Pending Publication Date: 2020-07-28
SUZHOU R&D CENT OF NO 214 RES INST OF CHINA NORTH IND GRP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The invention uses a high-precision peak detection module to detect the peak voltage, which consumes a lot of power and has a large area, and is not suitable for use as a pixel-level peak protection circuit.

Method used

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  • Pixel-level high-speed narrow-pulse peak holding circuit
  • Pixel-level high-speed narrow-pulse peak holding circuit
  • Pixel-level high-speed narrow-pulse peak holding circuit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0021] Such as figure 1 As shown, the pixel-level high-speed narrow pulse peak hold circuit includes a transimpedance amplifier, a comparator, a D flip-flop, an analog switch K, a holding capacitor C and a voltage follower. Transimpedance Amplifiers and Comparators The transimpedance amplifiers and comparators of the lidar readout circuit can be utilized. The input terminal of the transimpedance amplifier is connected to the current signal IN, the output terminal is connected to the non-inverting input terminal of the comparator, the inverting input terminal is connected to the threshold voltage VTH of the comparator, the output terminal of the comparator generates a digital signal STOP, and the digital signal STOP is connected to the D trigger at the same time The clock signal end of the D flip-flop, the D end of the D flip-flop is connected to the power supply VDD, the output end of the D flip-flop is connected to the analog switch K, the output end of the transimpedance amp...

Embodiment 2

[0025] Such as figure 2 As shown, on the basis of Embodiment 1, a voltage-controlled delay unit, a capacitor C1, MOS transistors M1, M2 and a resistor R1 are added.

[0026] Usually, the transimpedance amplifier needs to work in the linear region to ensure that the output voltage VA and the input current IN have a linear relationship. At this time, the pulse width of the input current IN is basically the same as the pulse width of the output voltage VA. However, when the input current IN is large, the transimpedance amplifier works in the nonlinear region, the voltage amplitude of VA is large, and the rising edge and pulse width of VA change.

[0027] At the output terminal VA of the transimpedance amplifier, add a capacitor C1, a plurality of series-connected gate-drain short-circuited MOS transistors M1, resistor R1, and MOS transistor M2 to sense the large-value voltage output at the VA terminal; at the output terminal of the comparator A voltage-controlled delay unit is...

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PUM

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Abstract

The invention discloses a pixel-level high-speed narrow-pulse peak holding circuit. A current signal IN is amplified by an transimpedance amplifier, the current signal IN is converted into a narrow pulse voltage signal VA; the voltage signal VA is compared with the threshold voltage of the comparator to generate a digital signal STOP, the digital signal STOP serves as the clock signal of the D trigger at the same time and is input to a node A through an analog switch K controlled by the output of the D trigger, the node A is grounded through a first capacitor C, and meanwhile the node A outputs a voltage OUT through a voltage follower. On the basis of the CMOS technology, further expansion is carried out on the basis of a pixel-level trans-impedance amplifier, and the peak value of the ns-level pulse width narrow pulse is kept. The peak holding circuit is extremely small in occupied area, low in power consumption and relatively high in holding precision.

Description

technical field [0001] The invention relates to a pulse peak holding circuit, in particular to a pixel-level high-speed narrow pulse peak holding circuit. Background technique [0002] The avalanche photodiode (APD) array has the characteristics of an all-solid-state structure, high quantum efficiency, and can maintain a good signal-to-noise ratio at high gain. The laser 3D imaging radar based on APD array uses laser to illuminate the target scene with flood light, and a 3D image of the target can be obtained with one laser pulse. When the bias voltage of the APD is lower than its avalanche voltage, it can linearly amplify the incident photoelectrons, and this working state is called the linear mode. In linear mode, the higher the reverse voltage, the greater the gain. The linear APD amplifies the input photoelectron with equal gain to form a continuous current, and obtains the laser continuous echo signal with time information and intensity information. [0003] The arra...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K5/1532
CPCH03K5/1532
Inventor 白涛
Owner SUZHOU R&D CENT OF NO 214 RES INST OF CHINA NORTH IND GRP
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