Lateral double-diffused transistor and manufacturing method thereof

Abstract

The invention provides a lateral double-diffused transistor and a manufacturing method thereof. The lateral double-diffused transistor comprises a substrate and a drift region located at the upper part of the substrate; a plurality of field oxide layers located on the surface of the substrate; a first N-type well region and a P-type well region which are located on the upper portion of the drift region and separated from each other, wherein the second N-type well region is adjacent to the P-type well region; a first gate oxide layer, a first polycrystalline silicon layer, a second gate oxide layer and a second polycrystalline silicon layer which are located on the surface of the substrate and cover part of the P-type well region; a first N+ region, a second N+ region and a third N+ regionwhich are respectively positioned in the first N-type well region, the P-type well region and the second N-type well region; a P+ region and a fourth N+ region which are located in the P-type well region, wherein the fourth N+ region is located on the two sides of the second polycrystalline silicon layer and located between the P+ region and the third N+ region. According to the lateral double-diffused transistor, different P+ regions and N+ regions are formed in the well region of the drift region, so that the conduction current of the device is improved, and the drain end current is controlled.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a lateral double-diffusion transistor and a manufacturing method thereof. Background technique [0002] As a kind of power field effect transistor, lateral double-diffused MOS (Lateral Double-Diffused MOSFET, LDMOS) transistor has been widely used because of its excellent thermal stability, high gain, and low thermal resistance. The performance requirements for LDMOS are also getting higher and higher, especially in UHV LDMOS (Ultra High Voltage Lateral Double Diffused Transistor). The main parameters to measure the performance of LDMOS are on-resistance and breakdown voltage. In practical applications, it is required to reduce the source-drain on-resistance Rdson as much as possible on the premise that the Off-BV (off-breakdown voltage) is sufficiently high. [0003] In order to obtain a higher Off-BV, the drift region of the conventional UHV LDMOS is very long, so its o...

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Problems solved by technology

Although this ensures that the conduction current of UHVLDMOS is increased without increasing the device area and without reducing the Off-BV, it increases the manufacturing cost of the chip, and the complex manufacturing process also makes the manufacturing cycle longer and the efficiency lower.

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