High-voltage-withstanding high-electron-mobility transistor

Abstract

The invention relates to a semiconductor power device, in particular to a transistor with high voltage resistance and high electron mobility. The transistor comprises a gate electrode, a source electrode, a drain electrode, a barrier layer, a channel layer, a nucleation layer and a substrate, wherein the channel layer is located between the barrier layer and the substrate, the channel layer comprises a P-type III-V group semiconductor layer, the projections of the nucleation layer and the drain electrode on the substrate at least partially coincide, the drain electrode is in electrical contactwith two-dimensional electron gas of the channel layer, the source electrode is in electrical contact with the P-type III-V group semiconductor layer, and the gate electrode is located on the barrierlayer.

Description

technical field [0001] The present application relates to semiconductor power devices, in particular, to a transistor with high withstand voltage and high electron mobility. Background technique [0002] Group III-V compound semiconductors include at least one group III element and at least one group V element, including but not limited to gallium nitride (GaN), aluminum gallium nitride (AlGaN), gallium arsenide (GaAs), indium nitride Aluminum gallium (InAlGaN), indium gallium nitride (InGaN), etc. Group III nitride semiconductors include nitrogen and at least one group III element, including but not limited to GaN, AlGaN, InN, AlN, InGaN, InAlGaN, etc. [0003] High electron mobility transistors (HEMTs) utilize III-V heterojunction structures, such as III-nitride heterojunctions, to generate two-dimensional electron gas (2DEG) at the heterojunction interface formed by III-nitride materials, which allows Through high current density and relatively low resistance loss, the w...

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Problems solved by technology

[0006] In comparison, if nucleation is formed from the gate or other regions and extended laterally, then the structures on both sides of the lateral epitaxy are basically symmetrical, which is not conducive to the formation of many asymmetric structures

And if the lateral epitaxy starts from the gate electrode area, the distance between the gate source and the gate drain is quite different, which is not conducive to making good use of the chip area.

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