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Structure for reducing b-c junction capacitance of heterojunction bipolar transistor and manufacturing method thereof

A technology of heterojunction bipolar and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, circuits, electrical components, etc., and can solve the problems of unfavorable highest oscillation frequency of current gain cut-off frequency and increase of base resistance Rb, etc.

Active Publication Date: 2021-07-06
XIAMEN SANAN INTEGRATED CIRCUIT
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The traditional method of reducing the b-c junction capacitance (Cbc) is to directly reduce the base metal width (WB) by photolithography to reduce the BC junction area (Abc) and achieve the effect of reducing the b-c junction capacitance (Cbc); but The reduction of the base metal width (WB) will lead to an increase of the base resistance Rb, which has an adverse effect on the current gain cutoff frequency (ft) and the maximum oscillation frequency (fmax) of the device

Method used

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  • Structure for reducing b-c junction capacitance of heterojunction bipolar transistor and manufacturing method thereof
  • Structure for reducing b-c junction capacitance of heterojunction bipolar transistor and manufacturing method thereof
  • Structure for reducing b-c junction capacitance of heterojunction bipolar transistor and manufacturing method thereof

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Embodiment 1

[0029] refer to figure 1 The process flow chart of , taking the base metal with a bottom line width of about 0.25 μm as an example, specifically illustrates a manufacturing method for reducing the b-c junction capacitance of a heterojunction bipolar transistor:

[0030] Firstly, a partially fabricated chip structure is provided, including an epitaxial layer 1 , an emitter structure (emitter platform 2 and emitter metal 3 ) and a passivation layer 4 . The process of the above structure refers to the known process, wherein after the emitter metal 3 is fabricated, a layer of 20-80nm SiN or SO is deposited using PVCVD 2 As a passivation layer 4, the resulting structure as figure 1 as shown in a;

[0031] Then, coat the first photoresist 5 with a thickness of 0.5-1.0 μm on the chip structure, the first photoresist 5 is a positive photoresist AR80 (from Tokyo Ohka), and use an I-line photolithography machine for exposure. TMAH (concentration 2.38%) developer is developed to obtai...

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Abstract

The invention discloses a structure for reducing the b-c junction capacitance of a heterojunction bipolar transistor and a manufacturing method thereof, and the method comprises the steps: firstly coating a chip structure with a first light resistor, exposing and developing the first light resistor to form a first window, then coating a second light resistor, and forming a second window; after the line width of the first window is reduced through a miniature and backflow process, etching the passivation layer in the first window to form a first opening, after the photoresist is removed, coating the passivation layer with a third photoresist, performing exposure and development to form a second window located on the first opening, wherein the line width of the second window is larger than that of the first opening; and depositing metal in the second window and the first opening to form base metal, and removing light resistance. The base metal structure with the bottom line width smaller than the top line width is formed, the b-c junction area is reduced under the condition that the base resistance is not increased, the effect of reducing the b-c junction capacitance is achieved, and therefore the highest oscillation frequency is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a structure and a manufacturing method for reducing b-c junction capacitance of a heterojunction bipolar transistor. Background technique [0002] With the development of HBT technology, higher requirements are put forward for high-frequency parameters. There are two main high-frequency parameters, one is the current gain cut-off frequency (ft); the other is the highest oscillation frequency (fmax). The maximum oscillation frequency (fmax) is inversely proportional to the product of base resistance (Rb) and b-c junction capacitance (Cbc), so in order to increase the maximum oscillation frequency (fmax), b-c junction capacitance (Cbc) and base resistance (Rb ). The traditional method of reducing the b-c junction capacitance (Cbc) is to directly reduce the base metal width (WB) by photolithography to reduce the BC junction area (Abc) and achieve the effect of reducing the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/331H01L21/28H01L29/423H01L29/737
CPCH01L29/66242H01L21/28H01L29/737H01L29/42304
Inventor 何湘阳郭佳衢魏鸿基
Owner XIAMEN SANAN INTEGRATED CIRCUIT
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