Sampling hold circuit structure for realizing offset elimination function

Abstract

The invention relates to a sampling hold circuit structure for realizing a detuning elimination function, which comprises an operational amplifier, a first CMOS (Complementary Metal Oxide Semiconductor) transmission gate module and a detuning elimination module, the positive input end of the operational amplifier is connected with an input signal, and the output end of the operational amplifier is connected with the first CMOS transmission gate module; the negative input end of the operational amplifier is connected with the output end of the operational amplifier to serve as a unit gain buffer, the two ends of the offset elimination module are connected with the positive input end of the operational amplifier and the output end of the CMOS transmission gate module respectively, and the offset elimination module is used for eliminating the influence of offset voltage introduced by the operational amplifier. By adopting the sampling hold circuit structure for realizing the offset elimination function, the offset voltage error of the operational amplifier is eliminated, the design difficulty of the operational amplifier is reduced, and meanwhile, the cost is reduced. The large-size MP1 and MN1 and the minimum-size MP2 and MN2 are adopted, the high sampling speed is met, and meanwhile the precision of the whole analog-to-digital converter is guaranteed.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to the field of sample-and-hold circuits, in particular to a sample-and-hold circuit structure for realizing the function of eliminating offset. Background technique [0002] The circuit structure of the prior art such as figure 1 As shown, the input signal Vin is connected to the positive input terminal of the operational amplifier AMP1, and AMP1 is connected in the form of a unity gain buffer, and the output terminal of AMP1 is connected to the sampling capacitor Cs through the CMOS transmission gate composed of PMOS transistor P1 and NMOS transistor N1. CK1 and CK2 respectively control the gates of N1 and P1, CK1 and CK2 are in an inverse relationship, and CK1 generates CK2 through inverter I1. [0003] Due to the offset voltage of the operational amplifier AMP1, the output voltage of AMP1 is Vin-Vos1, where Vos1 is the offset voltage of AMP1, and the voltage value depends on ...

AI Technical Summary

Problems solved by technology

Among them, Vos1 is related to the gain of the operational amplifier AMP1. The larger the gain, the smaller the Vos1, but the more complex the structure of AMP1 will be designed, the higher the cost. At the same time, because Vos1 is also related to the matching of the device in the process of manufacturing, so Vos1 is a random quantity that is difficult to control

The error v0 introduced by the channel charge injection and clock feedthrough effect is related to the size of the CMOS switch, and usually want to fast sampling speed, will choose larger size P1 and N1 transistors, which will lead to larger v0

The above shortcomings will directly lead to a decrease in the accuracy of the entire analog-to-digital converter

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