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Infrared light-emitting diode epitaxial wafer and preparation method thereof

An infrared light-emitting and diode technology, which is applied in semiconductor devices, electrical components, circuits, etc., can solve the problems of lattice mismatch, unsatisfactory multi-quantum well layer quality, and low luminous efficiency of infrared light-emitting diodes, achieving less strain and defects Effect

Active Publication Date: 2021-08-06
HC SEMITEK SUZHOU
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] Due to the large lattice mismatch between the InGaAs well layer and the GaAs barrier layer in the multi-quantum well layer, it is easy to cause a large stress in the multi-quantum well layer, and the existence of stress further leads to more Defects, so that the quality of the final multi-quantum well layer is not ideal, and the luminous efficiency of infrared light-emitting diodes is low

Method used

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  • Infrared light-emitting diode epitaxial wafer and preparation method thereof
  • Infrared light-emitting diode epitaxial wafer and preparation method thereof
  • Infrared light-emitting diode epitaxial wafer and preparation method thereof

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Embodiment Construction

[0030] In order to make the purpose, technical solution and advantages of the present disclosure clearer, the implementation manners of the present disclosure will be further described in detail below in conjunction with the accompanying drawings.

[0031] figure 1 It is a schematic structural diagram of an infrared light-emitting diode epitaxial wafer provided by an embodiment of the present disclosure. Refer to figure 1 It can be seen that the embodiment of the present disclosure provides an infrared light-emitting diode epitaxial wafer. The infrared light-emitting diode epitaxial wafer includes a substrate 1 and an n-type AlGaAs current spreading layer 2, an n-type AlGaAs confinement layer 3, and a second layer stacked on the substrate 1 in sequence. A stress adjustment layer 4, a multi-quantum well layer 5, a p-type AlGaAs confinement layer 6 and a p-type AlGaAs current spreading layer 7. The multi-quantum well layer 5 includes a plurality of alternately grown InGaAs well ...

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Abstract

The invention provides an infrared light-emitting diode epitaxial wafer and a preparation method thereof, and belongs to the field of light-emitting diode manufacturing. A first stress adjusting layer is additionally arranged between an n-type AlGaAs limiting layer and a multi-quantum well layer, the stress adjusting layer comprises a first AlGaAsP layer or comprises a first AlGaAsP / GaInP superlattice; tensile stress can be accumulated when the first stress adjusting layer grows; the tensile stress can be counteracted by the pressure stress of the multi-quantum well layer; and therefore, the pressure stress in the finally obtained multi-quantum well layer is small, and the crystal quality of the multi-quantum well layer is improved to improve the luminous efficiency. When the first stress adjusting layer comprises the first AlGaAsP / GaInP superlattice, the first AlGaAsP / GaInP superlattice can release certain stress in the growth process, the quality of a bottom layer structure below the multi-quantum well layer is good, so that the crystal quality of the multi-quantum well layer can be further improved.

Description

technical field [0001] The disclosure relates to the field of light-emitting diode production, in particular to an infrared light-emitting diode epitaxial wafer and a preparation method thereof. Background technique [0002] Infrared light emitting diode is an important light source device, which is widely used in remote control, vehicle sensing, closed circuit television, etc. Infrared light emitting diode epitaxial wafer is the basic structure for preparing infrared light emitting diode. Infrared light-emitting diode epitaxial wafers usually include a substrate and an n-type AlGaAs current spreading layer, an n-type AlGaAs confinement layer, a multi-quantum well layer, a p-type AlGaAs confinement layer, and a p-type AlGaAs current spreading layer stacked on the substrate in sequence. The well layer usually includes InGaAs well layers and GaAs barrier layers alternately grown in multiple periods. [0003] Due to the large lattice mismatch between the InGaAs well layer and ...

Claims

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Application Information

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IPC IPC(8): H01L33/12H01L33/06H01L33/30H01L33/00
CPCH01L33/12H01L33/06H01L33/30H01L33/0062
Inventor 邢振远李彤王世俊曹敏孙建建
Owner HC SEMITEK SUZHOU
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