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Method for reducing photoresist poisoning through double-pattern process

A double-pattern and photoresist technology, which is applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as insufficient accuracy of graphic definition, affecting device performance, and failure to meet design requirements, etc.

Pending Publication Date: 2021-09-14
SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

It is well known that the diffusion of active nitrogen components in nitrogen-doped silicon carbide can poison the photoresist, which greatly affects the accuracy of the pattern defined by the photoresist; for example, photoresist poisoning causes insufficient pattern definition accuracy, resulting in double pass The critical dimension between the holes is reduced, which cannot meet the design requirements and seriously affects the device performance

Method used

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  • Method for reducing photoresist poisoning through double-pattern process
  • Method for reducing photoresist poisoning through double-pattern process
  • Method for reducing photoresist poisoning through double-pattern process

Examples

Experimental program
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no. 1 example

[0031] Such as figure 1 As shown, the present invention provides a kind of method that double patterning process reduces photoresist poisoning, comprises the following steps:

[0032] S1, deposit the first NDC layer, TEOS layer, ULK layer, second NDC layer, first NFDARC layer, TIN layer and second NFDARC layer in sequence according to the designed tape-out process;

[0033] S2, double hard mask exposure, exposure and etching of the first via hole, so that the second NDC layer is exposed on the side wall of the first via hole;

[0034] S3, performing silane plasma treatment;

[0035] S4. Execute the follow-up design tape-out process.

[0036] In addition, it should also be understood that although the terms "first", "second", etc. may be used herein to describe various elements, parameters, components, regions, layers and / or sections, these elements, parameters, components, Regions, layers and / or sections should not be limited by these terms. These terms are only used to di...

no. 2 example

[0038] The invention provides a method for reducing photoresist poisoning by a double patterning process, comprising the following steps:

[0039] S1, such as figure 2 As shown, the first NDC layer, TEOS layer, ULK layer, second NDC layer, first NFDARC layer, TIN layer and second NFDARC layer are sequentially deposited according to the designed tape-out process, and the second NDC layer is used as a hard mask layer ;

[0040] S2, such as image 3 and Figure 4 As shown, double hard mask exposure, exposure and etching of the first heavy via hole, so that the second NDC layer is exposed on the side wall of the first heavy via hole;

[0041] S3, performing silane plasma treatment;

[0042] S4. Execute the follow-up design tape-out process.

[0043]Wherein, the pressure range of the silane plasma treatment is 1torr-3torr, the helium flow rate is 100sccm-1000sccm, the temperature range is 350°C-400°C, and the high-frequency radio frequency range is about 100 watts-1000 watts ...

no. 3 example

[0045] The invention provides a method for reducing photoresist poisoning by a double patterning process, comprising the following steps:

[0046] S1, such as figure 2 As shown, the first NDC layer, TEOS layer, ULK layer, second NDC layer, first NFDARC layer, TIN layer and second NFDARC layer are sequentially deposited according to the designed tape-out process, and the second NDC layer is used as a hard mask layer ;

[0047] S2, such as image 3 with Figure 4 As shown, double hard mask exposure, exposure and etching of the first heavy via hole, so that the second NDC layer is exposed on the side wall of the first heavy via hole;

[0048] S3, performing silane plasma treatment;

[0049] S4. Execute the follow-up design tape-out process.

[0050] Wherein, the silane plasma treatment pressure range is 1 torr, 2 torr or 3 torr, the flow rate of helium is 100 sccm, 200 sccm, 300 sccm, 400 sccm, 500 sccm, 600 sccm, 700 sccm, 800 sccm, 900 sccm or 1000 sccm, the temperature r...

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Abstract

The invention discloses a method for reducing photoresist poisoning through a double-pattern process. The method comprises the following steps that a first NDC layer, a TEOS layer, a ULK layer, a second NDC layer, a first NFDARC layer, a TIN layer and a second NFDARC layer are sequentially deposited according to a design tape-out process; double hard mask exposure and first through hole exposure etching are carried out to make the second NDC layer exposed on the side wall of the first through hole; silane plasma treatment is carried out; and a subsequent design tape-out process is carried out. A nitrogen-doped silicon carbide film with more stable nitrogen components is obtained by performing post-treatment on the exposed nitrogen-doped silicon carbide film after the first through hole etching, so that photoresist poisoning is reduced, a free active nitrogen component and silicon free radicals are combined to generate a stable silicon nitride component of silicon-nitrogen bonding, the silicon nitride component is distributed inside and on the surface of the nitrogen-doped silicon carbide film, the diffusion of the active nitrogen component in the nitrogen-doped silicon carbide is effectively inhibited, and the photoresist poisoning phenomenon can be reduced. According to the invention, the accuracy of graphic definition can be improved, the device can meet the design requirement, and the device performance is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a process method for reducing photoresist poisoning in a double patterning process. Background technique [0002] With the development of integrated circuit manufacturing technology and the reduction of critical dimensions, many new methods have been applied to the device manufacturing process to improve device performance. NDC (silicon carbonitride) has a comparative The characteristics of large etching selectivity make NDC widely used as etching barrier layer and etching hard mask layer in various technology nodes of 55nm, 40nm, 28nm, 22nm, 14nm, 7nm and below. [0003] As the critical dimensions of each technology node continue to decrease, the demand for lithography accuracy is getting higher and higher. At the technology node stage of 22nm, 14nm, 7nm and below, the dual patterning process is widely used. The double patterning process is a technology that splits the d...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/027H01L21/033
CPCH01L21/0273H01L21/0337
Inventor 魏想
Owner SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD