Fully-depleted silicon-on-insulator substrate, transistor and preparation method and application thereof

Abstract

The invention relates to a fully-depleted silicon-on-insulator substrate, a transistor and a preparation method and an application thereof. The preparation method of the fully-depleted silicon-on-insulator substrate comprises the following steps: forming a silicon oxide layer on a back lining silicon layer; carrying out photoetching and etching to enable the silicon oxide to form a plurality of grooves, enabling the grooves to penetrate through the silicon oxide layer and penetrate into the back lining silicon layer, enabling the surface of the back lining silicon layer to be divided into a plurality of silicon lines, and enabling the silicon oxide layer to be divided into a plurality of silicon oxide lines; forming a silicon top layer, wherein the silicon top layer fills the groove and covers the silicon oxide lines; thinning the silicon top layer; coating photoresist on the surface of the silicon top layer, and patterning to expose the surface of the silicon top layer covering the silicon oxide lines and the spacing areas of the adjacent silicon oxide lines; carrying out oxygen injection; and then annealing to form a silicon oxide isolation layer. According to the manufactured substrate, a parasitic capacitance can be reduced, and the operation speed can be increased; electric leakage can be reduced, and power consumption is lower; the latch-up effect can be eliminated; the substrate pulse current interference can be inhibited; and meanwhile, a strain is introduced.

Description

technical field [0001] The invention relates to the field of semiconductor production technology, in particular to a fully depleted silicon-on-insulator substrate, a transistor and a preparation method thereof. Background technique [0002] As its core device, the non-planar Fin FET device structure has strong gate control ability and strong ability to suppress the short channel effect, but the process flow of the Fin FET device is complicated; compared with the three-dimensional Fin FET process, the planar SOI device process The number of photoresist plates is much less, the process is relatively easier, and the process cost is greatly reduced. However, how to manufacture SOI substrates with small parasitic capacitance and low leakage is still a difficult point. [0003] For this reason, the present invention is proposed. Contents of the invention [0004] The main purpose of the present invention is to provide a method for preparing a fully depleted silicon-on-insulato...

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Problems solved by technology

[0002] As its core device, the non-planar Fin FET device structure has strong gate control ability and strong ability to suppress the short channel effect, but the process flow of the Fin FET device is complicated; compared with the three-dimensional Fin FET process, the planar SOI device process The number of photolithography plates is much less, the process is relatively easier, and the process cost is greatly reduced

However, how to fabricate SOI substrates with small parasitic capacitance and low leakage is still a difficult point

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