Multi-core RISV-CPU simulator based on Rust

A simulator and multi-core technology, applied in the computer field, can solve the problems of module expansion, abnormal memory access, complex structure and other problems in unfavorable simulators, so as to reduce memory security problems, exercise programming ability, and improve robustness.

Pending Publication Date: 2021-11-05
SHENZHEN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] After analysis, the existing mature simulator has a large amount of code and complex structure, which is not conducive to the expansion of modules in the simulator
Moreover, there is currently no mature simulator implemented in a memory-safe lan

Method used

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  • Multi-core RISV-CPU simulator based on Rust
  • Multi-core RISV-CPU simulator based on Rust
  • Multi-core RISV-CPU simulator based on Rust

Examples

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Embodiment Construction

[0025] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangements of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

[0026] The following description of at least one exemplary embodiment is merely illustrative in nature and in no way taken as limiting the invention, its application or uses.

[0027] Techniques, methods and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such techniques, methods and devices should be considered part of the description.

[0028] In all examples shown and discussed herein, any specific values ​​should be construed as exemplary only, and not as limitations. Therefore, other instances of the exemplary embodiment may have dif...

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PUM

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Abstract

The invention discloses a multi-core RISCV (Reduced International Standard Control Virtualization) simulator based on Rust. The simulator comprises a plurality of Risc-V processing core modules, a bus module, a DRAM module, a CLINT module, a PLIC module and a UART module, wherein the Risc-V processing core modules are constructed based on a Risc-V open source instruction set and used for achieving instruction fetching, decoding and execution functions. The DRAM module is used for simulating a memory; the PLIC module is used for simulating a hard disk; the UART module is used for simulating external interruption or local interruption; and the bus module is used for controlling information interaction among the Risc-V processing core module, the bus module, the DRAM module, the CLINT module, the PLIC module and the UART module so as to realize conflict-free communication. According to the simulator provided by the invention, the characteristics of security, memory layout control and concurrency are emphasized by using the Rust language, the memory security during the simulator operation is improved, and the robustness is strong.

Description

technical field [0001] The present invention relates to the field of computer technology, more specifically, to a Rust-based multi-core RISCV-CPU simulator. Background technique [0002] RISC-V is an open instruction set architecture based on the principle of reduced instruction set computing. RISC-V has a simple structure, with only more than 40 basic instruction sets, and a total of dozens of instructions plus other modular expansion instructions. Because RISC-V has the advantages of complete open source, simple architecture, and easy portability, it has been widely used recently. [0003] The Rust language is a system programming language that focuses on safety, and its main features are fast running speed and memory safety. Rust guarantees memory and thread safety through an ownership model and type system, enabling it to eliminate memory-related errors at compile time, and has performance close to that of C or C++, so Rust has a growing user base. [0004] Simulator i...

Claims

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Application Information

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IPC IPC(8): G06F15/17G06F9/30
CPCG06F15/17G06F9/30003
Inventor 徐君蒋旭伍楷舜
Owner SHENZHEN UNIV
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