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Clock data recovery circuit, processing chip and display equipment

A clock data recovery and circuit technology, which is applied in the field of circuits, can solve the problems of poor flexibility of clock data recovery circuits and achieve the effect of improving flexibility

Pending Publication Date: 2021-12-31
上海顺久电子科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The invention provides a clock data recovery circuit, a processing chip and a display device to solve the problem of poor flexibility of the clock data recovery circuit in the prior art

Method used

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  • Clock data recovery circuit, processing chip and display equipment
  • Clock data recovery circuit, processing chip and display equipment
  • Clock data recovery circuit, processing chip and display equipment

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0141] Embodiment 1: The pulse width of the output pulse signal is halved.

[0142] circuit timing as Figure 9 shown. The control signal generation module outputs a fixed control signal. After the UP / DOWN pulse signals up_bbpd and dn_bbpd are shifted and registered, they are input to the output logic module. The logic unit processes the multi-phase clock signal ck to generate The duty ratio is 1 / 4, that is, the narrow pulse signal ck_sel with a rising edge width of 1 / 4 UI, and the UP / DOWN pulse signal is sampled with the ck_sel signal: when the ck_bbpd signal and the output UP / DOWN pulse width are high at the same time , the output signal is high, otherwise the output signal is low, completing the reduction of the pulse width.

Embodiment 2

[0143] Embodiment 2: The pulse width of the output pulse signal is widened so that the pulse width is 2 UI.

[0144] circuit timing as Figure 10 shown. After the UP / DOWN pulse signals up_bbpd and dn_bbpd obtained by comparing the data and the clock are shifted and registered, they are input to the second voting logic unit. The second voting logic unit votes on the two consecutive UP messages, and when the two are not 0, output a pulse signal with a pulse width of 2 UI, otherwise output 0, completing the widening of the pulse width.

Embodiment 3

[0145] Embodiment 3: adaptively adjust the pulse width, and the adjustment range is -1 / 4 to 2 UI.

[0146] First, use the control signal generation module voting circuit to vote on the 4 continuous pulse signals, and input the control signal obtained by voting into the sequential logic unit for generating the control signal. Figure 11 Provides an implementation of a sequential logic circuit, taking the UP pulse signal up_bbpd as an example: after the sequential logic unit performs logic operations on the voting result signals mode_fin and mode, it outputs control signals to control flip-flops, adders, Subtractors and selectors work.

[0147] The current time n working mode control signal up_sel n Input the adder or subtractor, after adding 1 or subtracting 1, output the new working mode control signal up_sel n+1 (When set is valid, the output working mode signal is the setting mode up_sel), control the output logic module, and complete the adjustment of the pulse w...

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Abstract

The invention discloses a clock data recovery circuit, a processing chip and a display device. A phase discriminator compares a reference clock signal with a data signal to generate an initial pulse signal; the pulse width adjusting circuit performs shift register processing on the initial pulse signal to generate a shift pulse signal and generates a target pulse signal based on a current working mode selection signal, the shift pulse signal and a reference clock signal, and the charge pump circuit performs charging and discharging according to the target pulse signal and outputs a voltage signal; the voltage-controlled oscillator outputs a reference clock signal according to the voltage signal. The clock data recovery circuit comprises the pulse width adjusting circuit capable of adjusting the initial pulse signal, and the circuit adjusts the initial pulse signal based on the reference clock signal, so that the pulse width of the pulse signal can be adjusted as required on the premise of not using an additional signal, the flexibility of the clock data recovery circuit is improved.

Description

technical field [0001] The invention relates to the technical field of circuits, in particular to a clock data recovery circuit, a processing chip and a display device. Background technique [0002] In recent years, with the rapid development of communication systems, the requirements for data transmission capacity and quality have been continuously improved. The ever-increasing data transmission speed puts forward higher requirements on the speed, accuracy and supported frequency range of the receiving end. [0003] As an important part of the data receiving circuit, the design of the clock data recovery (Clock and Data Recovery, CDR) circuit is very important. The CDR circuit will generate a clock synchronized with the received data, and provide digital signal and clock reproduction at the receiving stage. The CDR circuit is usually composed of a phase detector (Phase Detector, PD), a charge pump (Charge Pump, CP) and a voltage controlled oscillator ( Voltage Control, VC...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/085H03L7/089H03L7/099
CPCH03L7/085H03L7/099H03L7/0891
Inventor 夏梦真卢家付傅懿斌
Owner 上海顺久电子科技有限公司