Assembly line ADC background digital calibration method and device based on histogram statistics

Abstract

The invention discloses an assembly line ADC background digital calibration method and device based on histogram statistics, and the method comprises the steps of obtaining an output digital code of each stage of ADC in a multi-stage assembly line ADC, and taking the Nth stage of ADC as an ideal rear stage; counting a histogram of the digital code output by the ideal post-stage, and calculating a gain coefficient between the ADC of the ideal post-stage and the ADC of the previous stage according to the histogram; according to the gain coefficient, calibrating the output digital code of the former-stage ADC of the ideal later stage; and combining the calibrated ADC with the Nth-stage ADC, updating an ideal post-stage, and after each update, calibrating an output digital code of the previous-stage ADC until the output digital code is calibrated to the first-stage ADC so as to complete the background digital calibration of the multi-stage assembly line ADC. The method can be operated in the background and is easy to implement, the inter-stage gain error of the assembly line ADC can be remarkably reduced without additionally adding an analog circuit, the calibration precision is high, and the method has very important significance for improving the signal-to-noise ratio and the linearity of the assembly line ADC.

Description

technical field [0001] The invention belongs to the technical field of pipeline analog-to-digital converters, and in particular relates to a pipeline ADC background digital calibration method and device based on histogram statistics. Background technique [0002] Pipeline analog-to-digital converter (analog to digital converter, analog-to-digital converter) is a common structure for realizing high-speed and high-precision converters. , CCD image data processing, ultrasonic monitoring and other high-speed and high-precision fields are more and more widely used. Because of the existence of the gain error between the stages of the pipeline ADC, it has a very bad influence on the signal-to-noise ratio and linearity of the system. Therefore, it is necessary to calibrate the inter-stage gain of the multi-stage pipeline ADC. [0003] The prior art provides a pipelined ADC inter-stage gain calibration method. After the chip is taped out, firstly, the actual gain of the pipeline st...

AI Technical Summary

Problems solved by technology

[0004] However, the above method requires additional analog circuits, which increases system power consumption and algorithm complexity, and is a foreground calibration that requires a specific operating environment to implement, and the calibration performance cannot be guaranteed after the chip working environment changes

Due to the fixed circuit structure, the calibration accuracy of the pipeline ADC inter-stage gain is limited, which is not conducive to improving the signal-to-noise ratio and linearity of the ADC.

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