Semiconductor structure and forming method thereof, and semiconductor device and forming method thereof

[0018] Seen from the background art, a semiconductor structure formed currently still the problem of poor electrical properties. Causes of poor electrical properties of the semiconductor structure are combined with a semiconductor structure.

[0019] refer to figure 1 , figure 1 It shows a structural diagram of a semiconductor structure.

[0020] The semiconductor structure illustrating an LDMOS design, the semiconductor structure comprising: a substrate, formed adjacent to the well region 11 and the drift region 12 within the substrate; a gate structure 20, 11 in the well region and above the substrate 12 at the junction of the drift region; a source region 31, 20 located within the well region 11 side of the gate structure; drain region 32, the drift region 20 located on the other side of the gate structure 12 . Spacer layer 40, a top cover portion and the sidewall of the gate structure 20 and the left cover base of the gate structure; conductive structure 50, 40 positioned above the spacer layer and the spacer layer 40 covers.

[0021] I.e. the conductive field plate structure 50, the end of the field plate incorporated field plate introduced a new peak electric field ( figure 1 As shown in dashed box), resulting in a weak point at the edge of the device becomes easy to cause breakdown at the edge of the device.

[0022] In order to solve the technical problem, embodiments of the present invention provides a method of forming a semiconductor structure, without increasing the basis of the process, a dummy gate structure is formed is not ion-implanted, and the dummy gate structure, and a spacer layer formed between the substrate and the gate structure of the dummy gate structure, a common structure as a spacer between the conductive structure and the substrate, due to the structure at the edge of the dummy gate conductive structure, and are positioned the thickness of the spacer layer between the gate structure and said structure is smaller than the thickness of the dummy gate dummy gate structure, whereby the structure close to the thickness of the conductive isolation structure is greater than at the edge close to the center of the isolation structure of the conductive structure and the thickness of the field isolation structure the peak impact, thicker near the edges of the conductive structure of the isolation structure helps reduce the peak electric field at the edges of the conductive structure and improve the breakdown voltage at the edge of the conductive structure resistant to withstand; further, due to the conductive structure is formed on the spacer layer, the spacer layer structure as compared to the dummy gate conductive structure closer to the center, due to the thickness of the spacer layer located between the gate and the dummy gate structure is less than the dummy structure the thickness of the gate structure, it is possible to ensure that the edge of the conductive structure breakdown is not based on reducing the thickness of the spacer layer near the center of the conductive structure as much as possible, so as to increase the breakdown voltage of the semiconductor structure at the same time minimizing the on-resistance in without increasing the process, to optimize the electrical performance of the semiconductor structure, to reduce production costs.

[0023] In order to make the above objects, features, and advantages of the embodiments of the present invention, the specific embodiments of the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0024] Figures 2 to 8 It is a schematic structural diagram of a method of forming a semiconductor structure of a semiconductor structure of the present invention. The following detailed description will be provided in conjunction with the accompanying drawings of the semiconductor structure of the present embodiment of the invention.

[0025] refer to Figure 2 - Figure 4 Providing a substrate (shown in Figure 4 ) Is formed adjacent to the well region and the drift region 101 of the substrate 102 within the substrate, the well region 103 is formed on gate structure 101 and the substrate 102 at the junction of the drift region, dummy gate structure 109 and the drift region 102 is formed on the substrate.

[0026] The substrate used for the subsequent process of forming LDMOS provide internet.

[0027] In this embodiment, the substrate comprises a substrate 100.

[0028] In this embodiment, an LDMOS semiconductor transistor structure as an example, the planar LDMOS transistor, the substrate is a corresponding planar substrate.

[0029] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate, other substrate materials germanium substrate, a silicon germanium substrate, a silicon carbide substrate, a gallium indium gallium arsenide substrate or the like may also be the substrate, the substrate It can also be other types of silicon-on-insulator substrate, a germanium substrate, or the like on the insulator substrate.

[0030] 100 formed in the substrate adjacent the well region 101 and the drift region 102, the drift region having a first type ion 102, 101 having a second well region of the ion type, the first type of ions and a second conductivity type different ion.

[0031] The well region 101 and the drift region 102 are in contact with a channel of the transverse diffusion zone to form a channel having a concentration gradient, the drift zone 102 for receiving a larger partial pressure.

[0032] Specifically, in the present embodiment, the semiconductor structure is used to form an NLDMOS, the first ion is an n-type ion, and the n-type ions include one or more of phosphorus ions, arsenic ions and antimony ions. The second ion is a p-type ion, and the p-type ions include one or more of boron ions, gallium ions and indium ions.

[0033] When the semiconductor structure is used to form a PLDMOS, the first ion is a p-type ion, and the p-type ions include one or more of boron ions, gallium ions, and indium ions, and the second ion is N-type ions including one or more of phosphorus ions, arsenic ions, and antimony ions.

[0034] In a specific embodiment, the formation step of the substrate can include:

[0035] First, a substrate 100 is provided and a phase adjacent well region 101 and a drift region 102 are formed on the substrate 100.

[0036] The step of forming the well region 101 and the drift zone 102 includes forming a first injection mask layer (not shown), the first injection mask layer exposed a substrate to be formed; An injection of the substrate doped by the mask layer is doped, form a well region 101; after forming the well region 101, a second injection mask covering the well region 101 and exposing the substrate portion region is formed. The layer (not shown in the figure), the second implant mask layer exposes a substrate to be formed by a drift zone; the substrate exposed by the second injection mask layer is doped to form the first ion. The drift region 102 is described.

[0037] In the embodiment of the present invention, the substrate exposed by the first injection mask layer is doped with the first injection mask layer to form a well region 101. Ion injection has the characteristics of simple operation, low process cost.

[0038] In the embodiment of the present invention, the substrate exposed by the second injection mask layer is doped with the second implantation layer to form the drift zone 102. Ion injection has the characteristics of simple operation, low process cost.

[0039] In this embodiment, the first injection mask layer and the second implantation layer are respectively injected into the injection mask of the forming well region 101 and the drift region 102, respectively.

[0040] The first injection mask layer and the second implantation layer are those capable of functioning and easy removal, so that the other membrane layer is reduced when removing the first injection mask layer and the second injection mask layer. Structural damage.

[0041] In this embodiment, the material of the first injection mask layer and the second injection mask layer are organic materials such as Barc (Bottom Anti-Reflective Coating, Bottom Anti-reflection Coating) Materials, ODL (OrganicDielectric Layer, Organic) Dielectric layer) Material, photoresist, DARC (Dielectric anti-Reflectivecoating, dielectric anti-reflection coating) material, Duo (Deep UV Light Absorbing Oxide, Deep Uvue Light Absorption Oxidation) Materials or APF (Advanced Patterning Film, Advanced Film) material.

[0042] Next, a gate structure 103 is formed on the substrate at the border of the well region 101 and the drift region 102, and a pseudo gate structure 109 is formed on the substrate of the drift region 102.

[0043] Specifically, combined Figure 2 - Figure 4 In this embodiment, the step of forming the gate structure 103 and the dummy gate structure 109 includes:

[0044] First, a gate dielectric material layer 1031a is formed on the substrate 100, and the gate dielectric material layer 1031a covers the substrate 100;

[0045] Next, a gate material layer 1032a is deposited on the gate dielectric material layer 1031a, and the gate material layer 1032a covers the gate dielectric material layer 1031a;

[0046] The gate material layer 1032a and the gate dielectric material layer 1031a form a discrete first gate dielectric layer 1031 and the second gate dielectric layer 1091, and a first gate on the first gate dielectric layer 1031. The pole layer 1032 and the second gate layer 1092 located on the second gate dielectric layer 1091, the first gate dielectric layer 1031, and the first gate layer 1032 constitute the gate structure 103, the second gate The dielectric layer 1091 and the second gate layer 1092 constitute the pseudo gate structure 109.

[0047] In this embodiment, the process of the graphicized gate material layer and the gate dielectric layer is a dry etch process. The dry etching process has an anisotropic etching characteristic, which has better etching profile control, facilitating the morphology of the gate structure 103 and the dick gate structure 109 to meet the process requirements.

[0048] In the present embodiment, the first gate dielectric layer 1031 is silicon oxide, the first gate layer 1032 being polysilicon. In other embodiments of the invention, the first gate dielectric layer 1031 may also be silicon nitride, silicon oxynitride, silicon oxide or high K gate dielectric material. The first gate layer 1032 may be metal gate materials such as Al, Cu, Ag, Au, Pt, Ni, Ti, Co or W.

[0049] In this embodiment, the gate structure 103 is located at the junction of the drift region 102 and the well region 101 and covers the drift region 102 and a portion of the well region 101.

[0050] In this embodiment, the step of forming the gate structure 103 further comprises: forming a first side wall 110 covering the first gate dielectric layer 1031 and the first gate layer 1032 side wall. The first side wall 110 is located on the two opposite sidewalls of the first gate dielectric layer 1031 and the first gate layer 1032. During the formation of the semiconductor structure, the first side wall 110 acts on the sidewall of the gate structure 103 to protect the gate structure 103, and the first side wall 110 is also used to define the formation area of ​​the source region.

[0051] The process step to form the first side wall 110 includes forming a conformal covering the substrate 100, the first gate layer 1032 and the first gate dielectric layer 1031 side wall material layer (not shown in the figure) Out), and the etching process is used to remove the side wall material layer of the top of the first gate layer 1032 and the top of the substrate 100 to form a first side wall 110.

[0052] In the present embodiment, the first side wall 110 is silicon oxide. In other embodiments of the invention, the first side wall may also be silicon oxide, silicon nitride, silicon carbide, carbonitride, carbonitrous oxide, silicon oxynitride, boron nitride, boron nitride. One or more of them.

[0053] In this embodiment, the pseudo gate structure 109 is located on the substrate of the drift region 102.

[0054] In this embodiment, the step of forming the pseudo gate structure 109 further comprises: forming a second side wall 111 covering the second gate dielectric layer 1091 and the second gate layer 1092 side wall.

[0055] In the present embodiment, the second gate dielectric layer 1091 is silicon oxide, the second gate layer 1092 being polysilicon. In other embodiments of the invention, the second gate dielectric layer may also be silicon nitride, silicon oxynitride, silicon oxide or high K gate dielectric material. The second gate layer 1032 may also be metal gate materials such as Al, Cu, Ag, Au, Pt, Ni, Ti, Co or W.

[0056] Since the pseudo gate structure 109 includes a second side wall 111, the side slope of the dummy gate structure 109 can reduce the thickness of the pseudo gate structure 109 gradually increase in the direction away from the gate structure, which is advantageous to improve the breakdown of the semiconductor structure. Voltage.

[0057] The process step of forming the second side wall 111 includes forming a conformal covering the substrate 100, the second gate layer 1092, and the second gate dielectric layer 1091 side wall material layer (not shown in the figure). Out), and the etching process is used to remove the side wall material layer of the top of the second gate layer 1092 and the top of the substrate 100 to form a second side wall 111.

[0058] In the present embodiment, the second side wall 111 is silicon oxide. In other embodiments of the invention, the second side wall may also be silicon oxide, silicon nitride, silicon carbide, carbonitride, carbonitride oxide, silicon oxynitride, boron nitride, boron nitride. One or more of them.

[0059] In this embodiment, the first side wall 110 and the second side wall 111 are simplified using the same process to simplify the process. In the present embodiment, the pseudo gate structure 109 is the same as the structure of the gate structure 103, and the material can be formed while forming the gate structure 103, thereby simplifying the process step to reduce process cost.

[0060] In the present embodiment, in order to simplify the process, the gate structure 103 and the dummy gate structure 109 are simultaneously formed, thereby no need to increase the mask, and the process cost is lowered.

[0061] It should be noted that the first gate layer 1032 has a conductive demand, so after the graphical gate material layer 1032a and the gate dielectric material layer 1031a, the first gate layer 1032 and the first gate dielectric layer 1031 are formed. And form an isolation layer 107 (shown Image 6 Before it is, it also includes: doping the first gate layer 1032. Specifically, in the present embodiment, ionically implantation can be performed on the first gate layer 1032 of the gate structure, and the subsequent conductivity can be performed. Although the gate structure 103 and the pseudo gate structure 109 are simultaneously formed, the pseudo gate structure 109 is subsequently not ion implantation, thereby improving the isolation layer thickness of the edge of the conductive structure in the subsequent process.

[0062] Specifically, such as Figure 5 As shown, a process for doping the first gate layer 1032 includes: forming a mask layer on the substrate 100, the mask layer exposes the top of the first gate layer 1032 and covers the 所 栅The polar structure 109; in the mask layer as a mask, doped ions are injected within the first gate layer 1032; the mask layer is removed.

[0063] Specifically, impurities of the first conductivity type doped with the first gate layer 1032. In the present embodiment, the first conductivity type is a p-type, and the impurities of the doped first conductive type may be boron, gallium or indium or the like.

[0064] In this embodiment, the second gate layer 1092 has an insulating demand, and therefore, the second gate layer 1092 does not perform doping in this step.

[0065] like Figure 5 As shown in the present embodiment, while ion implantation of the first gate layer 1032, the pseudo gate structure 109 may be formed within the drift region 102 on one side of the gate structure 103. The drain region 105, the pseudo gate structure 109 and the drain region 105 intersect or partially overlap the projection in the direction perpendicular to the substrate 100. The drain region 105 is disposed within the drift region 102 away from one side of the gate structure, and the pseudo gate structure 109 and the leakage region 105 are perpendicular to the liner. The projection intersecting or partially overlapping in the direction of the bottom 100 can cause the pseudo gate structure 109 to isolate, and when the semiconductor device is energized, the subsequent conductive structure 108 (shown in Figure 8Middle) A transverse electric field is formed between the drain regions 105 such that the conductive structure 108 points the portion of the electric field of the region 105, reducing the electric field strength of the gate structure 103, ensuring that the subsequent formed conductive structure 108 functions to optimize the electric field distribution .

[0066] Of course, while forming the drain region 105, the source region 104 can also be formed within the well region 101 on one side of the pseudo gate structure 109.

[0067] Continue reference Figure 5 In this embodiment, the formation method of the semiconductor structure also includes:

[0068] The tip end of the well region exposed by the gate structure 103 is doped with the tip end of the well region exposed by ion implantation to form the doped region 106, the doping region 106 located in the source region 104. On the side of the gate structure 103. Ion injection has the characteristics of simple operation, low process cost.

[0069] In the present embodiment, the source region 104 is formed in the well region 101 of the preset region in the well region 101 of the preset region, thereby forming the leakage region 105 in the drift region 102 of the region, thereby avoiding the substrate 100 of other regions. Doped ions.

[0070] It should be noted that in the step of forming a drain region 105 in the drift region 102, a source region 104 is formed within the well region 101 on the other side of the gate structure 103, and the source region 104 and the leakage The region 105 is doped with a first ion.

[0071] When the semiconductor structure is operating, the source region 104 and the drain region 105 provide stress to the channel to increase the migration rate of the carriers in the channel.

[0072] The steps of forming the source region 104 and the drain region 105 include:

[0073] The occlusion layer (not shown) is formed on the drift region 102 and a well area, and the shutter layer covers the doping region 106, the pseudo gate structure 109, and the pseudo gate structure 109 and The substrate between the gate structures 103;

[0074] It should be noted that the order of forming the source region 104, the drain region 105, and the doped region 106 is not limited. In other embodiments, it is also possible to form a source region and a drain region to form a doped region. When the source region drain region is formed, when the doped region is formed, the occlusion layer covers the doped region of the predetermined region, the pseudo gate structure 109, and the pseudo gate structure 109 and the gate structure 103. The substrate between.

[0075] The doped mask is formed in the drift region 105 in the drift region 102 in the trap region 101 in the well region 101.

[0076] Specifically, the source region 104 is located in a well region 101 on the side of the gate structure 103, and the source region 104 is doped with a first ion; the leakage region 105 is located at the gate structure 103 In the drift zone 102, there is a first ion in the drain region 105; the doped ion type in the drain region 105 and the source region 104 is the same as the doped ion type in the drift region 102. .

[0077] In this embodiment, the semiconductor structure is NLDMOS, and the first ion in the source region 104 and the drain region 105 is n-type ions. In other embodiments, when the semiconductor structure is PLDMOS, the first ion in the source region and the drain region corresponds to a p-type ion.

[0078] After forming the source region 104 and the drain region 105, it is also necessary to form an isolation layer 107 on the substrate between the gate structure 103 and the pseudo gate structure 109 (eg Image 6 As shown, the isolation layer 107 is at least between the gate structures 103 and the dummy gate structure 109 and in contact with the gate structure 103 and the pseudo gate structure 109, respectively, located in the gate The thickness of the spacer layer between the structural and pseudo gate structures is smaller than the thickness of the pseudo gate structure.

[0079] By the isolation layer formed on the substrate formed between the gate structure and the gate structure and the dummy gate structure, it is located as the isolation structure between the conductive structure and the substrate. The edge of the conductive structure, and the thickness of the isolation layer between the gate structure and the dummy gate structure is smaller than the thickness of the dummy gate structure, thereby having a thickness of the isolation structure at the edge of the conductive structure is greater than near the conductive. The thickness of the isolation structure at the center of the structural center, while the thickness of the isolation structure affects the peak of the electric field, the thickness of the isolation structure at the edge of the conductive structure is thick, which is advantageous to reduce the peak of the electric field at the edge of the conductive structure, and improve the edge of the conductive structure. Breakfast voltage.

[0080] In one embodiment, in order to make the subsequent conductive structure 108 (shown Figure 8 The thickness of the isolation structure between the substrate 100 (refers to the overall thickness of the dummy gate structure 109 and the isolation layer 107) increasingly increasing in the direction of the center of the conductive structure 108, the isolation layer 107 also covers the side wall of the pseudo gate structure 109 and the sidewall of the gate structure 103. By covering the sidewall of the dummy gate structure, the side slope of the isolation layer 107 can slow down such that the isolating layer 107 of the conformal covering the pseudo gate structure 109 has a corresponding gentle slope at the same time, so that the The thickness of the isolation structure between the conductive structure 108 is gradually increased toward the thickness of the isolation structure between the drain region 105 and the substrate 100, further optimizing the breakdown voltage of the semiconductor structure.

[0081] Such as Image 6 As shown, in the present embodiment, the isolation layer 107 also covers the top portion of the dummy gate structure 109 and a portion of the gate structure 103. Thus, in the process of subsequent filling conductive structures 108, a short circuit caused by direct contact with the gate structure 103 can be avoided.

[0082] Specifically, the isolation layer 107 protesters cover the gate structure 103 and the sidewalls and portions of the pseudo gate structure 109.

[0083] Thus, in the direction of the center of the conductive structure, the overall thickness of the dummy gate structure 109 and the isolation layer 107 gradually increases.

[0084] In the present embodiment, the isolation layer 107 is a metal silicide barrier layer that does not react with a metal such as titanium or cobalt by a metal silicide barrier layer to prevent metal silicide in a portion of the region. In the present embodiment, the 107 material of the spacer layer is silicon oxide.

[0085] Continue reference Figure 7 The conductive structure 108 is formed on the isolation layer 108 that covers at least the sidewall adjacent to the pseudo gate structure 109 and the gate structure 103.

[0086] In this embodiment, the conductive structure 108 covers the sidewalls and portions of the pseudo gate structure 109 and the gate structure 103 such that the width of the conductive structure increases in the direction parallel to the substrate, and when the device is powered When the conductive structure 108 and the transverse electric field formed between the drain regions 105 have increased the conductive structure 108 to further focus on the partial electric field of the region 105, reduce the electric field strength of the gate structure 103, thereby further optimizing the internal electric field line distribution, improve the resistance Wear voltage.

[0087] After forming the conductive structure 108, the distance between the conductive structure 108 and the substrate 100 is the total thickness of the dummy gate structure 109 and the isolation layer 107, by using the dummy gate structure 109 and the gate structure 103 and the gate. The isolation layer 107 formed between the electrode structure 109 is commonly used as an isolation structure between the conductive structure 108 and the substrate 100, and is located at the edge of the conductive structure 108 due to the dummy gate structure 109, and is located in the gate. The thickness of the isolation layer 107 between the polar structure 103 and the pseudo gate structure 109 is smaller than the thickness of the pseudo gate structure 109, thereby having a thickness of the isolation structure at the edge of the conductive structure 108 is greater than near the center of the conductive structure 108. The thickness of the isolation structure, and the thickness of the isolation structure affects the peak of the electric field, the thickness of the isolation structure at the edge of the conductive structure is thick, facilitating the electric field peak at the edge of the conductive structure 108, and improves the breakdown voltage at the edge of the conductive structure 108. . Further, since the conductive structure 108 is formed on the isolation layer 107, the isolation layer 107 is closer to the center of the conductive structure 108, from the center of the gate structure 103 and the pseudo gate structure 109. The thickness of the isolation layer 107 is smaller than the thickness of the pseudo gate structure 109, and can reduce the thickness of the isolation layer 107 at the center of the conductive structure 108 at the center of the center of the conductive structure 108 to ensure that the conductive structure 108 is not observed. The breakdown voltage of the semiconductor structure minus the on-resistance, so that the electrical properties of the semiconductor structure are optimized on the basis of the process flow, and reduce production costs.

[0088] Such as Figure 7 As shown, the conductive structure 108 is formed after forming the isolation layer 107, further includes:

[0089] A dielectric layer 130 is formed on the substrate, the dielectric layer 130 covers the substrate 100 and the isolation layer 107.

[0090] The dielectric layer 130 is for providing a process platform for subsequent forming conductive structures, and by the dielectric layer 130 such that electrical isolation is achieved with other electrical connection structures. Therefore, the material of the dielectric layer 130 is a dielectric material.

[0091] In this embodiment, the material of the dielectric layer 130 is silicon oxide. In other embodiments, the material of the dielectric layer can also be other dielectric materials such as silicon nitride or silicon oxynitride.

[0092] The step of forming the dielectric layer 130 comprises forming a dielectric material layer (not shown) on the substrate and gate structure 103; a planarization process is formed to form a dielectric layer 130.

[0093] refer to Figure 7 The step of forming the conductive structure 108 includes etching the dielectric layer 130 to form a first trench 121 exposed by the isolation layer 107; filling the conductive material in the first trench 121 to form a conductive structure 108.

[0094] A conductive structure 108 is formed in the dielectric layer 130, and the bottom end of the conductive structure 108 is in contact with the isolation layer 107, respectively.

[0095] In this embodiment, the material of the conductive structure 108 is tungsten (W). In other embodiments, the material of the conductive structure may also be a conductive material such as Al, Cu, Ag or Au.

[0096] In this embodiment, the electrochemical plating process is filled with the electrically plating process. Electrochemical plating process is simple, fast deposition speed, low price, etc.

[0097] When the first trench 121 exposed to the separator layer is formed, the first through hole 122 is formed by etching the dielectric layer 130, and the first through hole 122 is respectively exposed, respectively, respectively, respectively, and the source region 104. , Drain region 105 or gate structure 103;

[0098] Fill the conductive material in the first through hole 122, forming a contact hole plug 120, each contact hole plug 120 is a source electrode electrically connected to the source region, a drain electrode electrically connected to a drain region, and a gate structure Electrically connected gate electrodes and ground electrodes electrically connected to the doped region.

[0099]In this embodiment, the dielectric layer 130 is etched by a dry etch process, and the first trench 121 and the first through hole 122 are formed. The dry etching process has an anisotropic etching characteristic, with better etching profile control, facilitating the form of the first trench 121 and the first through hole 122 to meet the process requirements, and is also advantageous Improve the removal efficiency of the dielectric layer 130. In the process of dry etching process, it is possible to separately at the top of the source region 104, the drain region 105, and the gate structure 103, which reduces the damage to other film layer structures.

[0100] The embodiment of the present invention also provides a semiconductor structure, please refer to Figure 9 , Figure 9 It is a schematic structural diagram of an embodiment of the semiconductor structure of the present invention.

[0101] Such as Figure 9 As shown, the semiconductor structure provided by the embodiment of the present invention includes:

[0102] The substrate, the substrate 600 of the substrate forms an adjacent well region 601 and the drift region 602, the well region 601 and the drift zone 602, and a gate structure 603 is formed on the linear structure 603. And a pseudo gate structure 609 is formed on the substrate 600 of the drift region 602;

[0103] The drain region 605 is located within the drift region 602 located on one side of the gate structure 603, which is perpendicular to the substrate. The projection in the direction of 600 intersects or partially overlapping;

[0104] The isolation layer 607 is located on the substrate between the gate structure 603 and the pseudo gate structure 609, and the spacer layer 607 is in contact with the gate structure 603 and the pseudo gate structure 609, respectively. The thickness of the isolation layer 607 located between the gate structure 603 and the dummy gate structure 609 is smaller than the thickness of the pseudo gate structure 609;

[0105] The conductive structure 608 is located on the substrate between the gate structure 603 and the pseudo gate structure 609, the conductive structure 608 covers at least the sidewall of the pseudo gate structure 609 and the gate structure 603. .

[0106] The semiconductor structure provided by the embodiment of the present invention is commonly used as a conductive structure and a substrate by using a tabular structure and a separator formed on the substrate between the gate structure and the dummy gate structure. The isolation structure is located at the edge of the conductive structure due to the pseudo gate structure, and the thickness of the isolation layer between the gate structure and the dummy gate structure is smaller than the thickness of the dummy gate structure, thereby near the conductive structure. The thickness of the isolation structure at the edge is greater than the thickness of the isolation structure at the center of the conductive structure, facilitating the peak value at the edge of the conductive structure, increasing the breakdown voltage at the edge of the conductive structure; further, due to the conductive structure is formed on the isolation layer On the upper and, the isolation layer is closer to the center of the conductive structure compared to the pseudo gate structure, and the thickness of the separator layer between the gate structure and the dummy gate structure is less than the thickness of the pseudo gate structure. On the basis of ensuring that the edge of the conductive structure is not broken-down, it is possible to improve the breakdown voltage of the semiconductor structure while improving the on-resistance while increasing the basis of the process flow while ensuring the thickness of the separatum layer at the center of the conductive structure. The electrical properties of the semiconductor structure are optimized.

[0107] In one embodiment, in order to make the isolation structure thickness between the conductive structure 608 and the substrate 600 (referring to the overall thickness of the dummy gate structure 609 and the isolation layer 607) in the direction along the center of the conductive structure 608 A more generous increase, the isolation layer 607 covers the side wall of the pseudo gate structure 609 and a side wall of the gate structure 603. By covering the sidewall of the dummy gate structure, the side slope of the isolation layer 607 can slow down such that the isolation layer 607 of the protocol covering the pseudo gate structure 609 has a corresponding gentle slope, making the The thickness of the isolation structure between the conductive structure 608 is gradually increased towards the isolation structure of the isolation structure 600 to the substrate 600, further optimizing the breakdown voltage of the semiconductor structure.

[0108] In another embodiment, the isolation layer 607 can also cover the top portion of the dummy gate structure 609 and a portion of the gate structure 603. Thus, in the process of subsequent filling conductive structures 108, a short circuit caused by direct contact with the gate structure 603 can be avoided in the process of subsequent filling conductive structure 108.

[0109] In this embodiment, the substrate includes a substrate 600 for providing a process platform for subsequent forming LDMOS.

[0110] In this embodiment, the LDMOS is a planar transistor with a planar transistor with a planar substrate as an example, the LDMOS being a planar transistor.

[0111] In this embodiment, the substrate 600 is a silicon substrate. In other embodiments, the substrate may also be a substrate of a ruthenium substrate, a stem silicon substrate, a silicon carbide substrate, a gallium arsenide substrate or a gallium indium indium substrate, the substrate. It is also possible to provide other types of substrates such as silicon substrates on the insulator or a ruthenium substrate on the insulator.

[0112] In the substrate forms a phase adjacent well region 601 and a drift region 602 having a first ion, the well region 601 has a second ion, the first ion and The electrically conductive type of the second ion is different.

[0113] The well region 601 and the drift region 602 are in contact with a channel of the transverse diffusion region to form a channel having a concentration gradient, the drift region 602 for receiving a larger partial pressure.

[0114] Specifically, in the present embodiment, the semiconductor structure is used to form an NLDMOS, the first ion is an n-type ion, and the n-type ions include one or more of phosphorus ions, arsenic ions and antimony ions. The second ion is a p-type ion, and the p-type ions include one or more of boron ions, gallium ions and indium ions.

[0115] When the semiconductor structure is used to form a PLDMOS, the first ion is a p-type ion, and the p-type ions include one or more of boron ions, gallium ions, and indium ions, and the second ion is N-type ions including one or more of phosphorus ions, arsenic ions, and antimony ions.

[0116] In this embodiment, the gate structure 603 is located at the junction of the drift region 602 and a well region 601 and covers the drift region 602 and a portion of the well region 601. The gate structure 603 includes a first gate dielectric layer and a first gate layer 6032 located on the first gate dielectric layer 6031.

[0117] In the present embodiment, the first gate dielectric layer 6031 is silicon oxide, the first gate layer 6032 being polysilicon. In other embodiments, the first gate dielectric layer may also be silicon nitride, silicon oxynitride, silicon oxide or high K gate dielectric material. The first gate layer may also be a metal gate material such as Al, Cu, Ag, Au, Pt, Ni, Ti, Co or W.

[0118] In this embodiment, the gate structure 603 also includes a first side wall 610. The first side wall 610 is respectively located on the first gate dielectric layer 6031 and the first gate layer 6032 on two opposing sidewalls. The first side wall 610 acts on the sidewall of the gate structure 603 to protect, the first side wall 610 is also used to define the formation region of the source region.

[0119] In this embodiment, the pseudo gate structure 609 includes a second gate dielectric layer 6091 and a second gate layer 6092 located on the second gate dielectric layer 6091.

[0120] In the present embodiment, the second gate dielectric layer 6091 is silicon oxide, the second gate layer 6092 being polysilicon. In other embodiments of the invention, the second gate dielectric layer may also be silicon nitride, silicon oxynitride, silicon oxide or high K gate dielectric material. The second gate layer 1032 may also be metal gate materials such as Al, Cu, Ag, Au, Pt, Ni, Ti, Co or W.

[0121] Since the pseudo gate structure 609 includes a second side wall 611, the side slope of the pseudo gate structure 609 can be slowed, so that the thickness of the dummy gate structure 609 gradually increases in the direction away from the gate structure, which is advantageous for the breakdown voltage of the semiconductor structure. .

[0122] In the present embodiment, the pseudo gate structure 609 is the same as that of the gate structure 603, and the material can be formed while forming the gate structure 603, thereby simplifying the process step to reduce process cost.

[0123] In an embodiment of the present invention, the doping region 606 is formed at a top of the drift region 602, and a second ion is doped in the doped region 606, and the leak region 605 and the drift region 602 have One ion, the second ion is different from the conductivity type of the first ion.

[0124] The semiconductor structure further includes a source region 604 located within a well region 601 on the other side of the gate structure 603.

[0125] The doped ion type in the source region 605 and the source region 604 is the same as the doped ion type within the drift region 602, and the source region 604 and the drain region 605 are doped with a first type. ion;

[0126] When the semiconductor structure is operated, the source region 604 and the drain region 605 provide stress to the channel to increase the migration rate of the carriers in the channel.

[0127] Specifically, the leakage region 605 is located in a drift region 602 on the gate structure 603, and the leak region 605 is doped with a first ion; the source region 604 is located at the gate structure 603 Inside the well region 601, there is a first ion in the source region 604.

[0128] In this embodiment, the semiconductor structure is NLDMOS, the source region 604 and the first ion in the drain region 605 are n-type ions. In other embodiments, when the semiconductor structure is PLDMOS, the first ion in the source region and the drain region corresponds to a p-type ion.

[0129] In this embodiment, the semiconductor structure also includes:

[0130] The doping region 606 is located at the tip end of the well region exposed by the gate structure, the doping region 606 located away from the gate structure 603, the doped region 606. Doped with a second ion. The doped region 606 is used to isolate adjacent devices.

[0131] In this embodiment, the material of the spacer layer 607 is silicon oxide. Silicon is a commonly used dielectric material, and has higher process compatibility, which facilitates the reduction of the process difficulty and process cost of forming the isolation layer; in addition, the dielectric constant of silicon oxide is small, and it is also advantageous Improve the effect of the isolation layer for isolating the adjacent device. In other embodiments, the material of the isolation layer may also be other dielectric materials such as silicon nitride or silicon oxynitride.

[0132] In this embodiment, the semiconductor structure further includes a dielectric layer 630, on a substrate exposed by the gate structure 603, and the dielectric layer 630 covers the gate structure 603.

[0133] The dielectric layer 630 is configured to realize electrical isolation between adjacent devices, and the material of the dielectric layer 630 is a dielectric material.

[0134]In the present embodiment, the material of the dielectric layer 630 is silicon oxide. Silicon is a commonly used dielectric material, and has a higher process compatibility, which facilitates the reduction of the difficulty and process cost of forming the dielectric layer 630; in addition, the dielectric constant of silicon oxide is small. It is advantageous to increase the action of the dielectric layer 630 for isolating the adjacent device. In other embodiments, the material of the dielectric layer may also be a silicon nitride or silicon oxynitride or the like.

[0135] In this embodiment, the conductive structure 608 covers the sidewalls and partial tops adjacent the pseudo gate structure 609 and the gate structure 603 such that the width of the conductive structure 608 increases in the direction parallel to the substrate 600. When the device is energized, the lateral electric field formed between the conductive structure 608 and the drain region 605 increases the conductive structure 608 further divides some electric field strength of the region 605 to reduce the electric field strength of the gate structure 603, thereby further optimizing the internal electric field distribution, Improve anti-tapping voltage.

[0136] In this embodiment, the material of the conductive structure 608 is W. In other embodiments, the material of the conductive structure may also be a conductive material such as Al, Cu, Ag or Au.

[0137] In this embodiment, the semiconductor structure further includes a contact hole plug 620, the contact hole plug comprising a source electrode, a drain electrode, a ground electrode, and a gate electrode, respectively, respectively, and the source region 604, a drain region 605, The miscellaneous region 606 and the gate structure 603 are electrically connected.

[0138] Please refer to Figure 10 , Figure 10 It is a flow chart of a semiconductor device forming method according to an embodiment of the present invention. Such as Figure 10 As shown, the embodiment of the present invention also provides a method of forming a semiconductor device, including:

[0139] Step S10: Provides a first semiconductor structure and a second semiconductor structure that is a semiconductor structure formed by forming a method of forming the aforementioned semiconductor structure, and the working voltage of the first semiconductor structure is greater than the second semiconductor structure. Operating voltage.

[0140] It should be noted that the first semiconductor structure can be the same as the second semiconductor structure, and the first semiconductor structure may be different from the second semiconductor structure, and as long as the operating voltage of the first semiconductor structure is greater than the working voltage of the second semiconductor structure.

[0141] In this embodiment, the first semiconductor structure and the second semiconductor structure are the LDMOS transistor as an example, the LDMOS as a planar transistor, and the corresponding substrate is a planar substrate.

[0142] Step S20: Connect the gate structure of the first semiconductor structure and the gate structure of the second semiconductor structure.

[0143] Step S30: Connect the source of the first semiconductor structure and the conductive structure of the second semiconductor structure.

[0144] Step S20 and step S30 are not limited.

[0145] Due to the source of the first semiconductor structure and the conductive structure of the second semiconductor structure, the gate structure of the first semiconductor structure is connected to the gate structure of the second semiconductor structure, that is, the gate of the first semiconductor structure. The polar structure is associated with the gate structure of the second semiconductor structure, and when the gate structure of the first semiconductor structure is turned off, the conductive structure in the second semiconductor structure functions The effect, the thickness of the conductive structure and the substrate gradually increases in the direction along the center of the conductive structure to the edge, so that the electric field peak at the edge of the conductive structure can be reduced, and it is possible to not be broken at the edge of the conductive structure. On the basis, the isolation layer thickness is lowered, thereby increasing the breakdown voltage of the second semiconductor structure; when the gate structure of the first semiconductor structure is in communication with the gate structure of the second semiconductor structure, the operating voltage of the first semiconductor structure The working voltage greater than the second semiconductor structure, thereby forming a potential difference between the substrate of the conductive structure and the second semiconductor structure, resulting in aggregation of the drift zone surface, forming a low-impedance passage on the surface of the drift region, thereby reducing the second semiconductor structure liner Attachment resistance.

[0146] It can be seen that the method of forming the semiconductor device provided by the embodiment of the present invention is connected to the first semiconductor structure, not only optimizing the breakdown voltage of the second semiconductor structure, but also reduces the second semiconductor structure. The on-resistance.

[0147] Please refer to the map Figure 11 , Figure 11 It is a schematic structural diagram of a semiconductor device of the embodiment of the present invention. Such as Figure 11 As shown, embodiments of the present invention also provide a semiconductor device, including:

[0148] The first semiconductor structure 1 and the second semiconductor structure 2 are semiconductor structures formed by forming the aforementioned semiconductor structure, and the working voltage of the first semiconductor structure 1 is greater than the second semiconductor structure. 2 working voltage;

[0149] The gate structure 10 of the first semiconductor structure 1 is connected to the gate structure 20 of the second semiconductor structure 2;

[0150] The source 40 of the first semiconductor structure 1 is connected to the conductive structure 30 of the second semiconductor structure 20.

[0151] The semiconductor device provided in the embodiment of the present invention is connected to the first semiconductor structure, which is capable of optimizing the breakdown voltage of the second semiconductor structure, but also reduces the on-resistance of the second semiconductor structure.

[0152] For details on the specific description of the first semiconductor structure and the second semiconductor, please refer to the forebase, and details are not described herein again.

[0153] Although the embodiment of the present invention is disclosed, the embodiment of the present invention is not limited thereto. In any of the art, those skilled in the art can make various fracture and modifications without departing from the spirit and scope of the embodiments of the invention, and therefore the scope of protection of the embodiments of the present invention should be based on the scope of the claims.