Double-trapezoid-groove protection trapezoid-groove silicon carbide MOSFET device and manufacturing method thereof

A technology of trapezoidal grooves and silicon carbide, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems that the power density of devices cannot be increased, and the process technology of super junction MOS tubes is complicated, so as to avoid early breakdown , Improving the short-circuit tolerance capability and improving the effect of electron mobility

Active Publication Date: 2022-02-18
深圳真茂佳半导体有限公司
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Among them, the planar MOS transistor structure is to design the source contact and the drain contact on the same surface of the semiconductor substrate. With the development of the trend of wafer thinning and device miniaturization, the problem of leakage current from the back of the wafer will become more and more serious. It is a difficult problem that needs to be faced and overcome; trench MOS transistors are limited by the silicon limit, which leads to the inability to increase the power density of devices with the same on-resistance occupying a larger wafer area; and the process technology of super junction MOS transistors is too complex

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Double-trapezoid-groove protection trapezoid-groove silicon carbide MOSFET device and manufacturing method thereof
  • Double-trapezoid-groove protection trapezoid-groove silicon carbide MOSFET device and manufacturing method thereof
  • Double-trapezoid-groove protection trapezoid-groove silicon carbide MOSFET device and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0089] The application will be described in further detail below in conjunction with the accompanying drawings.

[0090] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are only part of the embodiments for understanding the inventive concepts of the present invention, and cannot represent All the embodiments are not explained as the only embodiment. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art on the premise of understanding the inventive concepts of the present invention fall within the protection scope of the present invention.

[0091] It should be noted that if there is a directional indication (such as up, down, left, right, front, back...) in the embodiment of the present invention, the directional indi...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention relates to a double-trapezoid-groove protection trapezoid-groove silicon carbide MOSFET device and a manufacturing method. The MOSFET device comprises a drain electrode substrate located at the bottom, a drain electrode epitaxial layer located in the middle, a source electrode metal layer located at the top, a grid electrode strip embedded in the drain electrode epitaxial layer and a drain electrode metal layer located at the bottom of the drain electrode substrate. The gate strip is arranged in the first groove with the inverted trapezoidal section in the drain epitaxial layer and is insulated through the interlayer film strip and the gate dielectric layer; a redefined channel layer is formed along the contour surface of the first groove so as to conduct the source metal layer and the drain metal layer; and a buffer layer is formed along the contour surface of the second groove with the inverted trapezoidal section in the drain electrode epitaxial layer, so that PN junction isolation is formed between the source electrode metal layer and the drain electrode extension layer. According to the invention, the electron flow of the drain substrate and the top surface source electrode can uniformly reach each region of the drain electrode metal layer.

Description

technical field [0001] The present application relates to the field of semiconductor transistors, in particular to a silicon carbide MOSFET device with double trapezoidal grooves protecting trapezoidal grooves and a manufacturing method. Background technique [0002] Silicon carbide belongs to the third-generation semiconductor material because of its wide bandgap (bandgap greater than 2.2eV), high thermal conductivity, high breakdown field strength, high electron saturation rate and high radiation resistance , can achieve better electron concentration and motion control, and is more suitable for making electronic devices used in high temperature, high pressure, high frequency, strong radiation and high power. [0003] At present, MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, Metal-Semiconductor Field-Effect Transistor) devices have a variety of structures, mainly including the following types: planar MOS tube, trench MOS tube and super junction MOS tube . Amo...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): H01L29/78H01L29/06H01L29/417H01L29/423H01L21/336
CPCH01L29/7811H01L29/7813H01L29/0642H01L29/4236H01L29/42376H01L29/41766H01L29/0611H01L29/0657H01L29/66068
Inventor 任炜强
Owner 深圳真茂佳半导体有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products