Manufacturing method of semiconductor structure and semiconductor structure

Abstract

The invention provides a manufacturing method of a semiconductor structure and the semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method of the semiconductor structure comprises the steps of providing a substrate; a plurality of active columns arranged in an array are formed on the substrate, each active column comprises a first section, a second section and a third section which are connected in sequence, and in the second direction, the cross section area of the second section is smaller than the cross section area of the first section and the cross section area of the third section; gate oxide layers are formed on the side wall of the second section, the top surface of the first section and the bottom surface of the third section; a gate dielectric layer is formed on the gate oxide layer, the length of the gate dielectric layer is smaller than that of the gate oxide layer, and the gate dielectric layer is arranged close to the third section. According to the semiconductor structure, the gate dielectric layer is formed on the side wall of the gate oxide layer, the length of the gate dielectric layer is smaller than that of the gate oxide layer, and the gate dielectric layer is close to the third section, so that the turn-off current of the semiconductor structure can be controlled, the problems of drain electrode leakage current induced by the gate electrode and inter-band tunneling can be reduced, and the performance and yield of the semiconductor structure can be effectively improved.

Description

technical field [0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor structure and the semiconductor structure. Background technique [0002] Dynamic random access memory (DRAM for short) is a semiconductor memory capable of writing and reading data at high speed and randomly, and is widely used in data storage devices or devices. Wherein, the DRAM includes a plurality of memory cells repeatedly arranged, and each memory cell includes a transistor and a capacitor, and the capacitor is connected to the source and drain of the transistor through a capacitive contact area and a capacitive contact structure. With the development of electronic products becoming lighter, thinner, shorter and smaller, the design of DRAM components is also developing towards the trend of high integration, high density and miniaturization. [0003] With the development of semiconductor technology, the size of...

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Problems solved by technology

[0003] With the development of semiconductor technology, the size of semiconductor devices is getting smaller and smaller, and problems such as Gate Induced Drain Leakage (GIDL) will have a greater adverse effect on the formation of semiconductor structures, reducing the performance of semiconductor structures. and yield

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