Method for improving scribing edge breakage

Abstract

The invention discloses a method for improving scribing edge breakage, which comprises the following steps of: 1, wafer preparation: selecting an MCZ silicon single crystal wafer with a 5-inch crystal orientation lt; 111gt, 111gt; the resistivity is 5.0-6.5 ohm / cm, and the thickness is 220 [mu] m + / -10%; step 2, scribing channel doping: phosphorus liquid state source deposition is carried out under the working conditions that the furnace temperature is 1120 DEG C, oxygen is 2L / min, nitrogen is 3L / min and source-carrying nitrogen is 1.2 L / min; the phosphorus source is propelled under the working conditions that the furnace temperature is 1140 DEG C, the oxygen is 2.5 L / min, and the nitrogen is 4L / min; four probes are used for testing the diffusion square resistance of 0.6 omega + / -10% and the junction depth of 12 microns + / -10%, a high-concentration impurity doping procedure is carried out on a scribing channel region, and a scribing channel becomes loose, so that scribing edge breakage and the severity of lattice damage caused by the scribing edge breakage are reduced, and the scribing quality of a wafer is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor chip design and manufacture, in particular to a method for improving chipping during scribing. Background technique [0002] The typical structure of a regular planning film track is as follows: figure 1 As shown, after the semiconductor wafer is manufactured, it is necessary to separate the individual chips by means of grinding wheel cutting, and the grinding wheel used for cutting is composed of hard corundum and adhesives, and the grinding wheel rotates at high speed to the wafer Cutting road for abrasive cutting. Since the wafer is made of silicon material, it has high hardness and high brittleness, and it will crack during the cutting process, such as figure 2 As shown, this phenomenon is called "collapsing edge" in the industry. [0003] Since the silicon atoms of monocrystalline silicon are arranged continuously in the order of the lattice, the chipping phenomenon will extend the ...

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Problems solved by technology

[0003] Since the silicon atoms of monocrystalline silicon are arranged continuously in the order of the lattice, the chipping phenomenon will extend the lattice damage to the inside of the silicon chip. If it extends to the effective working area of ​​the chip, it will lead to the failure of the chip's electrical parameters, so chipping It is a major factor leading to chip loss after dicing

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