Clock-driven FPGA chip global layout method based on multi-electric-field model

Abstract

The invention discloses a clock-driven FPGA chip global layout method based on a multi-electric field model. The method comprises the following steps: respectively establishing electric field models for density distribution of various different device types; inputting a circuit netlist obtained after logic synthesis and layout limitation of the FPGA chip, so that a layout result which is beneficial to meeting clock routing limitation in a legalization stage is generated in a global layout stage; converting the constrained non-convex optimization model into an unconstrained non-convex optimization model; and solving the constraint uniformly by adopting a nested optimization framework method, namely realizing the clock-driven FPGA chip global layout based on the multi-electric-field model. In addition, the method also adopts an algorithm structure suitable for the GPU to perform parallel computation, and the GPU can be fully utilized to perform accelerated computation, so that a better layout result meeting clock routing limitation is efficiently obtained in a global layout stage, and the quality and effect of the global layout of the FPGA chip are improved.

Description

technical field [0001] The invention belongs to the technical field of Electronic Design Automation (hereinafter referred to as EDA), relates to a global layout technology for Field Programmable Gate Array (hereinafter referred to as FPGA) in the physical design of chip integrated circuits, and specifically relates to a A clock-driven FPGA global layout method based on a multi-electric field model system. Background technique [0002] An FPGA is a semi-custom integrated circuit chip with programmable features that is pre-designed on a silicon chip. In the FPGA chip manufacturing process, the manufacturer will design the programmable gate logic device on the silicon chip in advance; when the customer uses the process, the designer can describe the customized logic circuit through hardware description language (Verilog or VHDL), and then use the hardware description language (Verilog or VHDL) to describe the customized logic circuit. EDA software such as logic synthesis, plac...

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Problems solved by technology

[0006] (1) Existing FPGA layout tools do not work well on large-scale FPGA layout problems

The existing FPGA layout tools mainly use the global layout algorithm based on quadratic programming. However, with the continuous increase of chip size and chip complexity, the FPGA global layout algorithm based on quadratic programming cannot achieve very good results in large-scale FPGA layout problems. good layout quality

[0007] (2) Existing FPGA global layout algorithms seldom consider restrictions on clock signal routing in the global layout stage

Due to the lack of restrictions on clock signal routing in the layout stage, the position of some devices that violate the clock signal routing needs to be adjusted in the later legalization stage, which will affect the quality of the entire layout result

[0008] In summary, the existing traditional FPGA global layout algorithm is difficult to achieve good layout results on large-scale FPGA layout problems, and because the restrictions on clock signal routing are less considered in the global layout stage, the legalization in the later stage of layout Adjustment of devices in stages that violate clock routing signals can affect placement quality

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