Integrated circuit layout method and layout device

Abstract

The invention relates to a layout method and a layout device of an integrated circuit. The layout method of the integrated circuit comprises the following steps that a layout is provided, the layout comprises a first element area and a second element area, and a spacer area is arranged between the first element area and the second element area; whether the width of the interval area is smaller than a preset width or not is detected, if yes, at least one of the first element area, the second element area and the interval area is marked, the preset width refers to the minimum width meeting the requirement, and the requirement is that the interval area is filled with at least one virtual pattern. According to the method, the element area with poor placement position in the layout can be quickly and accurately positioned, the layout efficiency of the integrated circuit is improved, the layout accuracy is improved, and a foundation is laid for improving the photoetching quality, shortening the development period of the integrated circuit, improving the yield of semiconductor products and the like.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a layout method and a layout device for an integrated circuit. Background technique [0002] A dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor device commonly used in electronic equipment such as computers, and it is composed of a plurality of repeated storage units, and each storage unit usually includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the opening and closing of the transistor, so that the stored data can be read through the bit line. Data information in the capacitor, or write data information into the capacitor. [0003] With the continuous shrinking of DRAM process nodes, the requirements for lay...

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Problems solved by technology

[0005] The invention provides a layout method and a layout device of an integrated circuit, which are used to solve the problem of low layout efficiency of the existing integrated circuit, to improve the layout accuracy, improve the quality of photolithography, shorten the development cycle of the integrated circuit, and improve Yield of semiconductor products

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