Electromagnetic compatibility comprehensive test system and method for semiconductor device drive circuit

Abstract

The invention provides an electromagnetic compatibility comprehensive test system and method for a semiconductor device driving circuit, the system comprises an electromagnetic disturbance module, a probe module, an oscilloscope module, an upper computer module and a test management module, the test management module is used for setting a protection threshold and a measurement coordinate, and is also used for counting and displaying a measurement result; the electromagnetic disturbance module is used for applying electromagnetic disturbance to the driving board; the probe module is used for moving a probe according to the set measurement coordinate, positioning a measurement point and automatically measuring an electric quantity signal on the semiconductor device driving board; the oscilloscope module is used for receiving the measured electric quantity signal and displaying a result; and the upper computer module is used for detecting and judging the electric quantity signal. Specific electric signals on the power semiconductor device driving circuit can be collected and measured, and influence rule analysis of external electromagnetic disturbance on the working state of the power semiconductor device driving circuit can be achieved.

Description

technical field [0001] The invention belongs to the technical field of semiconductor device testing, in particular to an electromagnetic compatibility comprehensive testing system and method for driving circuits of semiconductor devices. Background technique [0002] Since the on-off control of the press-contact integrated gate power semiconductor device needs to be realized through the cooperation of different circuits, the control logic of the drive circuit is relatively complex and is easily affected by external electromagnetic interference. When the drive circuit of the press-fit integrated gate power semiconductor device is subjected to conduction disturbances such as static electricity, surges, electrical fast transient bursts, and power frequency magnetic fields, problems such as false triggering and false reporting may occur. In order to improve the design rationality, control stability and working reliability of the drive circuit of the press-fit integrated gate pow...

AI Technical Summary

Problems solved by technology

[0003] The existing electromagnetic compatibility test platform can perform electrostatic discharge immunity, electrical fast burst immunity, surge immunity, voltage sag / short interruption / voltage change immunity and workability for the driving circuit of power semiconductor devices. However, there are still three main problems: (1) lack of specific electrical signal acquisition tools on the drive circuit of power semiconductor devices

Due to the small drive circuit and dense components of power semiconductor devices, it is impossible to use the voltage and current probes of conventional oscilloscopes to perform real-time detection and data acquisition of specific electrical signals on the drive board, and then obtain measurement data; only rely on the drive circuit of power semiconductor devices Status indicator for working status judgment

(2) The influence of external electromagnetic disturbance on the working state of power semiconductor device drive circuit is not clear

Due to the lack of necessary acquisition and measurement tools, the existing power semiconductor device drive circuit electromagnetic compatibility test can only judge whether the test is passed, but cannot obtain the specific electrical signal on the power semiconductor device drive circuit, and thus cannot deeply analyze the impact of external electromagnetic disturbance on the power semiconductor device. Influence law of driving circuit working state

(3) Electromagnetic compatibility test-simulation-design does not form a closed loop

Due to the lack of specific electrical signals on the power semiconductor device drive circuit, the EMC simulation results of the drive circuit cannot be compared with the EMC test results, and the optimized design cannot be initially verified through EMC simulation, which is not conducive to the high efficiency of the power semiconductor device drive circuit. optimized design

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