Semiconductor device

A semiconductor and component technology, applied in the field of semiconductor components, to achieve the effect of reducing inactive current and suppressing substrate current
CN1324716CInactive Publication Date: 2007-07-04KK TOSHIBA
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Patent Information

Authority / Receiving Office
CN Β· China
Patent Type
Patents(China)
Current Assignee / Owner
KK TOSHIBA
Publication Date
2007-07-04
Estimated Expiration
Not applicable Β· inactive patent

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Abstract

A semiconductor device comprises a semiconductor substrate having a main surface; a semiconductor layer of a first conduction type provided on the main surface of said semiconductor substrate; a first buried layer of the first conduction type provided between said semiconductor layer and said semiconductor substrate; a first connection region of the first conduction type provided around said first buried layer, said first connection region extending from the surface of said semiconductor layer to said first buried layer; a switching element provided in the surface region of said semiconductor layer on said first buried layer; and a low breakdown-voltage element provided in a surface region of said semiconductor layer, said low breakdown-voltage element being closer to said first connection region than said switching element and having lower breakdown voltage than that of said switching element.
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Description

technical field

[0001] The present invention relates to semiconductor elements. Background technique

[0002] In the past, LDMOS (Lateral Double Diffused Metal Oxide Semiconductor) was frequently used in power integrated circuits. LDMOS is a semiconductor device capable of switching large currents.

[0003] FIG. 8 is a circuit diagram of a general power switch circuit using LDMOS. The power switch circuit adopts a synchronous rectification power supply mode. The power supply of the high voltage Vcc is connected to the drain electrode of LDMOS1, and the ground GND is connected to the source electrode of LDMOS2. Between LDMOS1 and LDMOS2, current is supplied from node N to the load through a filter.

[0004] An input signal is supplied to gate electrodes of LDMOS1 and LDMOS2 through a control circuit. The control circuit controls the input IN1 of LDMOS1 and the input IN2 of LDMOS2 so that LDMOS1 and LDMOS2 are not turned on at the same time.

[0005] When LDMOS1 is in th...

Claims

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